Comments (5)
Ok, thank you.
If you still plan to include the file for PULPissimo builder or any other, you could create another pull request. The branch name is "pulpissimo_integration".
from scr1.
Potentially, we don’t mind, - please, submit your pull request for review. We may need to keep PULPissimo-related changes in a dedicated branch, - hope that’s fine?
Best regards,
Kate
from scr1.
Yeah, it would be even better. This way I could include a src_files.yml
file, so that PULPissimo builder can easily recognize it. For now I'll send just code though.
from scr1.
I'll let you know here, when there will be some development in upstream PULPissimo.
from scr1.
Sure, thank you for merging.
from scr1.
Related Issues (20)
- Syntacore custom modification problems HOT 3
- SCR bootloader’s banner does not show up after I RESET the Arty A7-100T board. HOT 5
- The behavior of Stepping through DCSR.step and DMCONTROL.resumereq HOT 2
- Error 'make tests' fails HOT 1
- Verilator timing required? HOT 1
- Error: unrecognized opcode `fence.i' HOT 17
- Error running Coremark benchmark HOT 7
- Coremark testcase still failed after added #9 issue solution HOT 4
- Invalid result of `DIV` operation HOT 3
- How does it work for sc_print to print words in terminal when running HDL simulator? HOT 2
- AXI Interconnect problems HOT 3
- Error when running Dhrystone HOT 2
- Incorrect linker flags' order into make file HOT 1
- Incorrect linker flags' order into make file
- Unaligned data access exceptions are not reported in simulation HOT 2
- [question][help wanted] always_ff multiple procedure assignment at scr1_memory_tb_ahb.sv HOT 1
- Segmentation fault HOT 2
- Got an error while performing coremark test
- store instructions may fail when a CSR is written HOT 6
- mstatus register resets once the breakpoint hits HOT 9
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