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13.0 13.0 7.0 6.65 MB

License: BSD 2-Clause "Simplified" License

VHDL 88.22% Python 0.06% Shell 0.09% C 0.24% Tcl 0.50% Verilog 10.34% SystemVerilog 0.53%

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felixkubicek avatar laurivosandi avatar szanni avatar

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aeshw's Issues

Use second AMBA interconnect

Hi,

I noticed your project on your blog and after working on it I noticed that you used the first AMBA interconnect to build your crypto core. This bus is used by all others peripherals so the crypto core could be slower.

I noticed in the Zybo reference doc that there is a second AMBA interconnect available with AXI high performance ports (Cf page 5 on 26). I looked at the dts file where bus and peripherals are set but there is nothing about this second interconnect (which could be faster and less used).

Do you know if there is a way to use it ? Could it improve the crypto core performances ?

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