t-head-semi / thead-extension-spec

T-head vendor extension Instruction Set spec

T-Head ISA extensions (Xthead*)

This repository contains the T-Head RISC-V ISA extensions (Xthead*) specifications.

Build instructions

The specification is written in AsciiDoc. The following instructions can be used to generate a PDF containing all specifications:

make

thead-extension-spec's Issues

cannot make pdf

Hi, my ruby version is 2.7.0 and when I use make to generate PDF, I got an error report:
/usr/lib/ruby/2.7.0/tempfile.rb:121:in `<top (required)>': superclass mismatch for class Tempfile (TypeError)
I am not familiar with Ruby, and I am at a loss for this.

incorrect ff0/ff1 operation

The Operation of ff0/ff1 is not correspond to Description. In ff0 process, it is supposed to check from 63 bit to 0 bit, and return from 0 to 63.

`XTheadMemIdx`: contradicting mnemonics

It seems instruction table and per-instruction description has different mnemonics.

For instance, from the instruction table,

RV32	RV64	Mnemonic	Instruction
Y	Y	th.lrb rd, rs1, rs2, imm2	Load indexed byte

But in section 9.1.23. th.lrb:

Mnemonic
th.lrb rd, (rs1), rs2, imm2

(both are quotes from version 2022-11-07 2.1.0)

Currently, GNU Binutils implements the former (without paren). But...

• At least, we should fix the manual for consistency (even if "no paren form" is correct) and
• If the latter mnemonic is the correct format (like other XTheadMemIdx instructions like th.lbia), GNU Binutils should be fixed (I can handle that).

`XTheadFMemIdx`: No parens?

As I pointed out in #6, there are some inconsistencies in XTheadMemIdx.

XTheadFMemIdx does not have such inconsistencies in the manual but replacing rs1 with (rs1) may be an option to keep consistency with other RISC-V instructions.

Is not having parens around rs1 is intentional? If not, we should fix both the manual and GNU Binutils (I can handle the GNU Binutils part).

PDF release would be convenient

Suggest a link from README.md to where a pre-compiled PDF can be downloaded.