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License: MIT License
This project forked from kayaleitner/fpga_mnist
License: MIT License
This is a bit ugly and maybe it's not a good idea to have an array in the sensitivity list
update_weights : process (w_i)
-- # TODO This is a bit ugly and maybe it's not a good idea to have an array in the sensitivity list
begin
for i in 0 to FILTER_WIDTH - 1 loop
for j in 0 to FILTER_HEIGHT - 1 loop
2484e0fbb5ee30a3d70e41911af0cfda595f7526
This needs to be generic in one step
-- NN ALU
------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nnpkg.all;
-- NN ALU Component
entity nn_alu is
generic (
PARALLEL_INPUT : natural := 3;
INPUT_BITS : natural := 8;
WEIGHT_BITS : natural := 8;
OUTPUT_BITS : natural := INPUT_BITS + WEIGHT_BITS
-- OUTPUT_BITS : natural := INPUT_BITS + nlog2(PARALLEL_INPUT) -- prevent overflow
);
port (
clk : in std_logic;
rst : in std_logic;
-- SWITCH
-- mode : in std_logic;
-- x_i : in std_logic_vector(0 to PARALLEL_INPUT - 1, INPUT_BITS - 1 downto 0);
x_i : in vec1d_t(0 to PARALLEL_INPUT - 1)(INPUT_BITS - 1 downto 0);
w_i : in vec1d_t(0 to PARALLEL_INPUT - 1)(WEIGHT_BITS - 1 downto 0);
y_o : out std_logic_vector(OUTPUT_BITS - 1 downto 0)
);
end nn_alu;
architecture arch of nn_alu is
constant z1_ZERO : vec1d_t(0 to PARALLEL_INPUT - 1)(OUTPUT_BITS - 1 downto 0) := (others => (others => ('0')));
constant z2_ZERO : std_logic_vector(OUTPUT_BITS - 1 downto 0) := (others => '0');
signal z1 : vec1d_t(0 to PARALLEL_INPUT - 1)(OUTPUT_BITS - 1 downto 0) := z1_ZERO;
signal z2 : std_logic_vector(OUTPUT_BITS - 1 downto 0) := z2_ZERO;
begin
process (clk, rst)
variable temp : unsigned(INPUT_BITS - 1 downto 0);
begin
if rst = '1' then
z1 <= z1_ZERO;
z2 <= z2_ZERO;
elsif rising_edge(clk) then
-- MUL
MUL : for i in 0 to PARALLEL_INPUT - 1 loop
--z1(i) (OUTPUT_BITS -1 downto INPUT_BITS) <= (others => '0');
z1(i) <= std_logic_vector(unsigned(x_i(i)) * unsigned(w_i(i)));
--z1(i) (INPUT_BITS-1 downto 0) <= x_i(i);
end loop; -- MUL
-- ADD
-- # TODO This needs to be generic in one step
y_o <= std_logic_vector(unsigned(z1(0)) + unsigned(z1(1)) + unsigned(z1(2)));
end if;
end process;
end architecture; -- arch
No newline at end of file
ew file mode 100644
ndex 0000000..c878058
++ b/vivado/NN_IP/EggNet_1.0/concepts/nn_conv_kernel.vhd
00046f5f3f414f978c2d02a54a5d13a664039c4f
Reado Input exonent etc. from generator
vectors = EggUnit.get_vectors_from_image(images_c)
kernels = EggUnit.get_Kernels(vectors)
results = self._gen_Result_data(images)
super().load_testdata(kernels[:,:,:,:,:,0],"testdata.csv","TB_CSV_DATA_FILE")
super().load_testdata(results,"resultdata.csv","TB_CSV_RESULTS_FILE")
def _gen_Result_data(self, images):
# TODO: Reado Input exonent etc. from generator
conv_layer = Conv2d_shift_Layer(1,16,1,self.param_path, 8, 7, 6)
result = conv_layer(images.astype(np.uint8))
return result
def execute(self):
super().execute()
d9273c44549e3452acfb57decec8955ad0ae5000
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