Name: UCTECHIP
Type: Organization
Bio: UCTECHIP is an innovation startup firm in China, providing professional technical service on full solutions of SoC design and applications, focus on IP cores
Location: China, ShenZhen
Blog: www.uctechip.com
UCTECHIP's Projects
circuit described in Chisel, refer to chisel-template and chisel-tutorial
Converts ELF files to HEX files that are suitable for Verilog's readmemh.
Prebuilt GNU toolchain for RISCV Linux
QUICK_START for HWJ-SoC linux
patch for riscv-gnu-toolchain
RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
DejaGnu RISC-V port
RISC-V port of GNU's libc
GNU toolchain for RISC-V, including GCC
Spike, a RISC-V ISA Simulator
RISC-V port of newlib
Fork of OpenOCD that has RISC-V support
BBL for HWJ-SoC
Rocket Chip Generator
RT-Thread for LS
u-boot for HWJ-SoC
WH-SDK