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2023-05-03-yosys-lakeroad-demo

Demo of Yosys+Lakeroad integration for Yosys team.

3la-evaluation

3la-ir-example

Example showing the different stages of Relay and TVM IR for a single program.

3la-tvm

Fork of TVM for 3LA BYOC extensions

biovault_bfloat16

A bfloat16 implementation for BioVault projects

calyx

Intermediate Language (IL) for Hardware Accelerator Generators

calyx-evaluation

churchroad

circt

Circuit IR Compilers and Tools

dahlia

Time-sensitive affine types for predictable hardware generation

dtr

Dynamic Tensor Rematerialization

dtr-prototype

Dynamic Tensor Rematerialization prototype (modified PyTorch) and simulator. Paper: https://arxiv.org/abs/2006.09616

f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

firrtl-rust

Still work in progress (WIP)

flexgen

Running large language models on a single GPU for throughput-oriented scenarios.

lakeroad

FPGA synthesis tool powered by program synthesis

lakeroad-evaluation

lastlayer

Towards Hardware and Software Continuous Integration

libposit

A library for working with the posit number type.

marius

Large scale graph learning on a single machine.

nexus

nexus-artifacts

ps-lite

A lightweight parameter server interface

pytorch

Dynamic tensor rematerialization, implemented as a pytorch fork

pytorch-playground

Base pretrained models and datasets in pytorch (MNIST, SVHN, CIFAR10, CIFAR100, STL10, AlexNet, VGG16, VGG19, ResNet, Inception, SqueezeNet)

relay-aot

An experimental ahead of time compiler for Relay.

relay-bench

A repository containing examples and benchmarks for Relay.

relay-network

skywater-pdk-libs-sky130_fd_sc_hd

sofa

SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA