uwsampl / lakeroad-evaluation Goto Github PK

To summarize the question, the ExtractOp only takes a lowbit as an argument. The highbit is implicit. This raises to questions:

1. Is highbit determined as lowbit + output_type_size - 1?
2. If so, what if lowbit + output_type_size - 1 > input_type_size??

Her's a summary of ExtractOp's description and signature

• comb.extract (::circt::comb::ExtractOp):

  Extract a range of bits into a smaller value, lowBit specifies the lowest bit included.

  • Syntax:

     operation ::= `comb.extract` $input `from` $lowBit attr-dict `:` functional-type($input, $result)
    

We currently just don't do this.

For example, an integer divider is implemented with a fixed point divider. We pre-synth the fixed point divider, but we don't technically pre-synth the entire integer divider (though it will be mostly/all pre-synthed, because it's just a FP divider).

It's hard because we'd need to start importing modules, which gets messy quickly (try it and you'll see).

We are not presynthesizing memories in Calyx, namely because Calyx's test ecosystem is not set up for it. Calyx's tests depend on being able to look at the internal state of a memory.

It's kind of a lame excuse, but it's pretty important to know that Calyx is still functional, so I really don't want to break the tests permanently.

I looked at using something like the keep attribute in Verilog, but it doesn't preserve a signal all the way through place and route, which is what we need.

I want to get an end-to-end smoketest done and checked into the eval repo, just for my own sanity. Here's what I wanna do:'

• Ingest an ISA instruction (ideally multiple, but can start with one) expressed either in Rosette or translated to Rosette from Reticle/Comb/whatever
• Synthesize ISA instruction for Xilinx UltraScale+
• Compile synthesized result to Verilog implementation
• Place and route the result to ensure validity
  • Is this enough? It would be great to actually get it onto a board!
• Simulate the result with Verilator to ensure functional correctness
  • Is this enough?

• https://www.reddit.com/r/FPGA/comments/giz7k1/inference_of_subtract_in_dsp_48/
• https://www.reddit.com/r/FPGA/comments/14pd07x/how_does_multiplication_of_signed_vs_unsigned/

Once we have the data being generated, need to collect into a table.

We need to collect benchmarks for Lakeroad. This will be the primary source of documentation for finding benchmarks.

Possible benchmarks:

• Synopsys DesignWare
• OpenCores
  • Apparently there is a wide spectrum of quality on the designs in OpenCores. Improving an OpenCores design isn't necessarily an impressive thing; depends on the quality of the underlying design.
• Intel FPGA guys said they could give us some older networking cores
• Intel NPU
  • Specifically this module
• Pile of Cores (PoC)
• VHDL-extras
• libc in VHDL
• PCK_FIO from easics
• VHDL GitHub repositories from Martin J Thompson
• noasic from Guy Escheman
• open-vhdl
• general-purpose-fifo
• vhdl-examples
• vhdlbyexample
• vhdl-libs-pro
• hdl4fpga
• Aeroflex Gaisler
• Stefan VHDL
• BaseJump STL
  • We may actually want to use this repo
• OpenPiton
  • Similar to BaseJump, there is a repo with preconfigured sizes. Ask Dan.
• Instances of use_dsp = yes on GitHub
• These may be duplicates, I am moving them here from the Lakeroad meeting notes:
  https://github.com/ispras/hdl-benchmarks
  https://github.com/VLSI-EDA/PoC
  https://www.linkedin.com/pulse/poc-free-open-source-vendor-independent-ip-core-library-lehmann/
  https://github.com/intel/fpga-npu/blob/main/rtl/mvu_sched.sv
  https://github.com/intel/fpga-npu/blob/main/rtl/mvu_sched.sv
  https://github.com/intel/fpga-npu/tree/main/rtl

The ICmpOp takes a predicate argument, and I'm not sure how this is supposed to be interpreted. My guess is that it is just an int code to determine which comparison to run.

I've asked on the CIRCT discord but haven't gotten a response yet.

In the mean time I'm going to generate fresh source for common comparisons:

• ==
• !=
• is_zero
• is_not_zero
• >
• >=
• <
• <=

The task seems to fail in Docker, but I can't replicate on my Mac or on boba.

In the evaluation-results artifact I'm finding the next/nextpnr logs for lattice but we are not generating the baseline logs. @gussmith23 and I already chatted about this I think, but this is necessary for generating the resource usage and timing tables in the paper.

Currently we're not running the task that generates the Yosys table. I updated our Yosys+Lakeroad fork for the YosysHQ demo, but I haven't updated the eval to work on that updated version of Yosys+LR.

This is potentially a way to build a more robust evaluation. As far as I know, Yosys breaks up a design into subcomponents and then calls ABC on subcomponents to map. We could replace that call to ABC with a call to Lakeroad.

We currently don't use Calyx in the eval, so disable it for now (i.e. in the Docker build)

I ran into this problem a while ago. I started using route_design -release_memory because the flag prevented a crash in the Docker container. Turns out it prevents a crash because it doesn't run routing at all. Whoops.

Without the flag, we get the crash. So have to investigate this.

Currently blocked by gussmith23/lakeroad#150.

This behavior is misleading/annoying, ideally it would only generate valid Verilog files. This might be an issue for uwsampl/lakeroad instead.