ODIN II: Instantiating more than one module with dual_port_ram inside fails about vtr-verilog-to-routing

[kmurray]

Oops. Missing architecture file (taken from VPR directory)

Reported by eddie.hung on 2012-01-20 01:02:03

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- _Attachment: [sample_arch.xml](https://storage.googleapis.com/google-code-attachments/vtr-verilog-to-routing/issue-9/comment-1/sample_arch.xml)_

[kmurray]

Reported by jeffrey.goeders on 2012-01-20 18:17:44

• Labels added: Module-ODIN

[kmurray]

Thank you for discovering this issue. 

The problem stems from the fact that Odin II currently fails to prefix hard blocks
with the module instance name and simply uses the module name. The original author
of this code must have neglected to include the module instance name when naming the
hard blocks. 

I've got someone looking into it, so it should be fixed soon. 

Reported by andy16666 on 2012-04-18 12:17:13

[mflawn]

Issue unresolved

Attached file and sample_arch.xml to reproduce
test2.v.txt

./odin_II -V test2.v -a ../libs/libarchfpga/arch/sample_arch.xml  

	Optimizing module by AST based optimizations 
	Converting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)
	==========================
	Detected Top Level Module:      m
	==========================
	-------------- 
	Odin has decided you have failed ;)

	ERROR (1):NETLIST_ERROR (File: test2.v) (Line number: 41) Missing declaration of this symbol dual_port_ram
			  .addr2(addr2));
	ASSERT FAILED:
			@[/mnt/c/Users/casa/vtr-verilog-to-routing/ODIN_II/SRC/ast_util.cpp]get_name_of_pins::813
	Aborted (core dumped)

[jeanlego]

fixed