Comments (3)
This is something I would use as well. It makes the initial portion of the routing graph output a more complete description of the architecture for routing purposes. Note that there is no RELIABLE way of deducing the intended (non-clipped) length of a segment over arbitrary array sizes. Thanks.
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Agreed, let's do this. @amin1377 says he can get to it in the not-too-distant future.
from vtr-verilog-to-routing.
That's great news. Thank you.
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Related Issues (20)
- Upgrade Self-Hosted Runners to Node20 HOT 8
- Can Titan benchmarks be used for power analysis? HOT 4
- CI artifacts are not available for download when a CI test fails HOT 3
- Issue with git submodule update --init Command HOT 1
- Update documentation (and code if needed) to make placement constraints 3D HOT 1
- Update documentation for 3D arch switches
- Test rr-graph write out and read in with a 3D architecture.
- Prevent running the CI if only the docs are updated HOT 2
- Missing Output Port in BLIF File Generation Using ABC HOT 1
- Constant and inverter "replication" during packing HOT 2
- Remove has_path_to_sink HOT 1
- high fanout routing to heap code -- only count CHANX and CHANY nodes to determine if enough has been added. HOT 5
- Loosen the minimum channel width and related metric pass characteristics for small circuits HOT 1
- See if simplifying the placement cost function slightly would speed up placement.
- Document how to build for debugging HOT 2
- Missing documentaion for some 3D-related tags and fields in the architecture reference
- [Route] Precision Issues in the Connection Router HOT 6
- Relax when router lookahead issues warnings for failure to find sample locations HOT 5
- [CI] Nightly Test Failures HOT 2
- Passing only Fc max to pin to track map function HOT 1
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