Odin Doesn't Support Syntax for Escaped Verilog Identifiers about vtr-verilog-to-routing

[stefanpie]

I wanted to follow up on this pull request after some more experimenting:

1. There are other small Verilog syntax edge cases not supported by Odin that are defined in the Verilog 1995 standard.
2. I made a Verilog "preprocessing" Python module as a quick workaround that works for now.

Other Verilog Edge Cases
Odin II does not support spaces in integer literals. For example, the following integer literals will cause errors in Odin II.

32'h 0000_0000,
32'h ffff_ffff,
32'h 0000_0010,

However, if you remove the space from the integer literals, as shown below, Odin II can parse the Verilog without throwing those specific errors.

32'h0000_0000,
32'hffff_ffff,
32'h0000_0010,

For more details and examples, see section "2.5.1 Integer constants" of the Verilog 1995 standard (https://ieeexplore.ieee.org/document/803556).

Workaround Python Preprocessing Module
To workaround both the escaped identifier and integer literal parsing bugs in Odin II, I wrote a Python module that can "preprocess" Verilog source to transform it into Verilog that Odin II can currently parse. This seems to address the two main issues I am having at the moment, and I wanted to share this in case others come across this issue. See the attached zip file for the module code: verilog_preprocessor.zip. I use Python 3.10 with type annotations. The module only uses standard library imports and should work standalone.