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Library for Logic Synthesis and Optimization

CMake 0.02% C++ 5.40% C 0.34% Shell 0.01% Python 0.25% Lex 0.01% Yacc 0.05% Verilog 93.92%

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libmajesty's Issues

Useless branch kept

See pictures, here applying a Relevance action but can it happen for other actions as well? :
capture d ecran 2017-05-05 a 17 35 05

We get some orphaned nodes? :
capture d ecran 2017-05-05 a 17 35 13

First graph :

// Written by the Majesty Logic Package
module top (
			a , b , c , 
			F ) ;
input a , b , c ;
output F ;
wire w4 , w5 , w6 ;
assign w4 = ~a | b ;
assign w5 = c | ~w4 ;
assign w6 = ( a & b ) | ( a & ~w5 ) | ( b & ~w5 ) ;
assign F = ~w6 ;
endmodule

Second graph :

// Written by the Majesty Logic Package
module top (
			a , b , c , 
			F ) ;
input a , b , c ;
output F ;
wire w4 , w5 , w6 , w7 ;
assign w4 = ~a | b ;
assign w5 = c | ~w4 ;
assign w6 = ~b | c ;
assign w7 = ( a & b ) | ( a & ~w6 ) | ( b & ~w6 ) ;
assign F = ~w7 ;
endmodule

NB: graphs are equals

Swap move detection is messed up

Example Graph (ONE EXAMPLE IS NOT ENOUGH TO KNOW IF IT REALLY WORKS) :

capture d ecran 2017-05-05 a 19 08 38

get_moves and get_moves_fast do not even bring the same results....
get_moves seems to be the correct one, and get_moves_fast the incorrect one
capture d ecran 2017-05-05 a 19 08 46

The partial version gives a third different result which is the union of both outputs
capture d ecran 2017-05-05 a 19 20 06

// Written by the Majesty Logic Package
module top (
			a , b , c , 
			F ) ;
input a , b , c ;
output F ;
wire w4 , w5 , w6 , w7 , w8 , w9 ;
assign w4 = b & c ;
assign w5 = b & ~c ;
assign w6 = ~b | w4 ;
assign w7 = ~a & w5 ;
assign w8 = a & w6 ;
assign w9 = w7 | w8 ;
assign F = w9 ;
endmodule

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