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$ make overlay PFM=kv260_ispMipiRx_vcu_DP OVERLAY=alpr
Build alpr Vitis overlay using platform kv260_ispMipiRx_vcu_DP
make[1]: 进入目录“/home/pc/FPGA/KV260/kria-vitis-platforms/kv260/overlays/examples/alpr”
/nas/apps/Xilinx/Vivado/2022.2/bin/vivado -mode batch -source scripts/gen_dpu_xo.tcl -tclargs binary_container_1/dpu.xo DPUCZDX8G hw mpsoc

****** Vivado v2022.2 (64-bit)
  **** SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
  **** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

Sourcing tcl script '/home/pc/.Xilinx/Vivado/Vivado_init.tcl'
source scripts/gen_dpu_xo.tcl
# if { $::argc != 4 } {
#     puts "ERROR: Program \"$::argv0\" requires 4 arguments!\n"
#     puts "Usage: $::argv0 <xoname> <krnl_name> <target> <device>\n"
#     exit
# }
# set xoname    [lindex $::argv 0]
# set krnl_name [lindex $::argv 1]
# set target    [lindex $::argv 2]
# set device    [lindex $::argv 3]
# puts $xoname
binary_container_1/dpu.xo
# set suffix "${krnl_name}_${target}_${device}"
# source -notrace ./scripts/package_dpu_kernel.tcl
WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/pc/FPGA/KV260/kria-vitis-platforms/kv260/overlays/dpu_ip/Vitis/dpu/hdl/DPUCZDX8G.v'.
WARNING: [IP_Flow 19-5226] Project source file '/home/pc/FPGA/KV260/kria-vitis-platforms/kv260/overlays/dpu_ip/DPUCZDX8G_v4_0_0/ttcl/fingerprint_json.ttcl' ignored by IP packager.
WARNING: [IP_Flow 19-5101] Packaging a component with a SystemVerilog top file is not fully supported. Please refer to UG1118 'Creating and Packaging Custom IP'.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/arch_def.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "/home/pc/FPGA/KV260/kria-vitis-platforms/kv260/overlays/examples/alpr/dpu_conf.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1841] HDL Parser: Add include file "/home/pc/FPGA/KV260/kria-vitis-platforms/kv260/overlays/examples/alpr/dpu_conf.vh" to file group xilinx_anylanguagesynthesis.
INFO: [IP_Flow 19-1841] HDL Parser: Add include file "/home/pc/FPGA/KV260/kria-vitis-platforms/kv260/overlays/examples/alpr/dpu_conf.vh" to file group xilinx_anylanguagebehavioralsimulation.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/arch_para.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/function.vh" from the top-level HDL file.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/nas/apps/Xilinx/Vivado/2022.2/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'dpu_clk' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'dpu_clk' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'dpu_clk_dsp' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'dpu_clk_dsp' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'dpu_clk_dsp_ce' of definition 'xilinx.com:signal:clockenable:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'dpu_clk_dsp_ce' of definition 'xilinx.com:signal:clockenable:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'dpu_resetn' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'dpu_resetn' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute).
WARNING: [IP_Flow 19-1654] Cannot find bus abstraction "deephi:dpu:reg_thd:1.0" from the IP catalog.
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_GP0' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_HP0' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_HP1' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_HP2' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_HP3' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'dpu_clk': Added interface parameter 'ASSOCIATED_CLKEN' with value 'dpu_clk_dsp_ce'.
INFO: [IP_Flow 19-4728] Bus Interface 'dpu_clk_dsp': Added interface parameter 'ASSOCIATED_CLKEN' with value 'dpu_clk_dsp_ce'.
INFO: [IP_Flow 19-4728] Bus Interface 'dpu_clk': Added interface parameter 'ASSOCIATED_RESET' with value 'dpu_resetn'.
INFO: [IP_Flow 19-4728] Bus Interface 'dpu_clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'M_AXI_GP0'.
INFO: [IP_Flow 19-4728] Bus Interface 'dpu_clk_dsp_ce': Added interface parameter 'POLARITY' with value 'ACTIVE_HIGH'.
INFO: [IP_Flow 19-4728] Bus Interface 'dpu_resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
WARNING: [IP_Flow 19-5661] Bus Interface 'dpu_clk_dsp' does not have any bus interfaces associated with it.
WARNING: [IP_Flow 19-731] File Group 'xilinx_anylanguagesynthesis (Synthesis)': "/home/pc/FPGA/KV260/kria-vitis-platforms/kv260/overlays/examples/alpr/dpu_conf.vh" file path is not relative to the IP root directory.
WARNING: [IP_Flow 19-4816] The Synthesis file group has two include files that have the same base name. It is not guaranteed which of these two files will be picked up during synthesis/simulation:   src/dpu_conf.vh
  /home/pc/FPGA/KV260/kria-vitis-platforms/kv260/overlays/examples/alpr/dpu_conf.vh
WARNING: [IP_Flow 19-731] File Group 'xilinx_anylanguagebehavioralsimulation (Simulation)': "/home/pc/FPGA/KV260/kria-vitis-platforms/kv260/overlays/examples/alpr/dpu_conf.vh" file path is not relative to the IP root directory.
WARNING: [IP_Flow 19-4816] The Simulation file group has two include files that have the same base name. It is not guaranteed which of these two files will be picked up during synthesis/simulation:   src/dpu_conf.vh
  /home/pc/FPGA/KV260/kria-vitis-platforms/kv260/overlays/examples/alpr/dpu_conf.vh
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [IP_Flow 19-795] Syncing license key meta-data
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/nas/apps/Xilinx/Vivado/2022.2/data/ip'.
ERROR: [Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

    while executing
"source -notrace ./scripts/package_dpu_kernel.tcl"
    (file "scripts/gen_dpu_xo.tcl" line 31)
INFO: [Common 17-206] Exiting Vivado at Mon Mar 13 09:57:53 2023...
make[1]: *** [Makefile:67：binary_container_1/dpu.xo] 错误 1
make[1]: 离开目录“/home/pc/FPGA/KV260/kria-vitis-platforms/kv260/overlays/examples/alpr”
make: *** [Makefile:61：overlays/examples/alpr/binary_container_1/link/int/system.bit] 错误 2