Author: Mariano Leonel Acosta
Date: March 2018
In this project I designed a Digital to Analog Converter in VHDL. It comes handy for FPGA development boards that lacks a D/A. Particularly, I used it on the Zybo board from Digilent.
data: Signed integer (24 bits)
clk: Clock Signal
dac_out: Binary (1 bit). Pulse Density Modulation (PDM) Signal. In order to recover the baseline signal, this output has to be low-pass filtered in the analog domain.