Tiny RISC V CPU based on TinyRV2 as listed here: https://www.csl.cornell.edu/courses/ece4750/handouts/ece4750-tinyrv-isa.txt
This CPU is designed as a basic non pipelined CPU that can be further expanded on.
Currently the CPU should work if given proper inputs.
Still need to write test cases and figure out someway to get outputs off of CPU.