zeeshanrafique23 / rv32i-logisim

RV32I single cycle simulation on open-source software Logisim.

RV32I-Logisim

Introduction

Logisim allows you to design and simulate digital circuits. It is intended as an educational tool, to help you learn how circuits work. This is the implementation of RISC-V base ISA RV32I.

Pre-requisites

You need to install Logisim and Java Run-time Environment to run the simulation on logisim by running the following commands.

For Ubuntu run the following set of commands.

sudo apt install logisim; sudo apt install default-jre; java -version

Design

This implementation can help the beginners of RISC-V to get started. The circuit includes

• PC
• Register File
• ALU
• ALU Control
• Control Unit
• Immediate generation
• Memories (data and inst)

Top level diagram

rv32i-logisim's Issues

Immediate generation double shifting.

I'm finding really helpful this project to understand a basic implementation of a RISC-V core but I'm having some trouble trying to understand the use of a shifter for the B-type and J-type instruction formats. The standard talks about "shifting" 1 bit at the time that the relocation of the bits is being done, thing that you also do.

The only difference between the S and B formats is that the 12-bit immediate field is used to **encode
branch offsets in multiples of 2 in the B format

And

Similarly, the only difference between the U and J formats is that the 20-bit immediate is shifted
left by 12 bits to form U immediates and by 1 bit to form J immediates.

The circuit on your project that I'm talking about:

Is doing a double shift an error or I am not seeing something?