zipcpu / axidmacheck

AXI DMA Check: A utility to measure DMA speeds in simulation

AXI DMA Check

This is a basic AutoFPGA connected design for the purpose of testing various open source data mover solutions.

The data movers, together with the AXI interconnect and the various AXI bus bridges and helpers, can be found in the wb2axip project. (Expect this to become a submodule to this project, since it needs to be downloaded into the main directory.)

Reconfigure

To reconfigure the project, adjust the AutoFPGA scripts listed in autodata/Makefile, and run make autodata. You will need AutoFPGA built and installed somewhere in your path. Note: Only the dev branch of AutoFPGA currently contains AXI support.)

Simulation

To build the design, run make rtl; make sim. You will need to have Verilator installed. Running the simulation is as easy as cd sim/; ./main_tb. There's not much to see, however, unless you run ./main_tb -d instead to produce a VCD file. There's also a GTKWave file which you can use when viewing the VCD file to help get some clarity to what's going on early on.

You can also run the simulation using make test. A similar main directory make coverage will build a set of HTML files which can be used to evaluate test coverage.

License

This design is licensed under the GPL. It is not intended to be an end user design--the RAM core consists of a large block RAM, the streams are quite void of any useful information, etc. Indeed, this design makes a better example of what can be done using Verilator rather than an end design in itself, and so the GPL license (a primarily software license) seems to fit a simulation only project the best.

The core and guts of this project come from the WB2AXIP project which is (currently) available under an Apache license. AutoFPGA is licensed under GPL, although the designs created with it are free for licensing as you see fit.

axidmacheck's Issues

Enhancement Request for Ephemeral Working Directory

Issue - invoking the "autofpga" make target results in changes to git status. Intentional manual changes by a developer to the repo may be camouflaged by the automatic changes.

Request - instead of modifying in place the files under rtl/, sim/, and sw/, copy these directories to an ephemeral directory (e.g. ./tmp/) and work with them there. The imported wb2axip and dbgbus repositories would also go into the ephemeral directory.

Regards,
Bob

Details:
https://github.com/ZipCPU/autofpga commit f89d4dce81baed312c843c8554923fee7750d0a1
https://github.com/ZipCPU/axidmacheck commit 4e7923d

make coverage command which found some error to create html coverage files

`/axidmacheck/sim$ ./main_tb -d

Opening Bus-master with
VCD File = trace.vcd
AXIMM2S Check:
BEATS: 0x00002000
CLOCKS: 0x00002000
COUNTS: 0x00002031
AXIMM2S (abort) Check:
BEATS: 0x000002f7
CLOCKS: 0x000002f7
COUNTS: 0x00000328
AXIMM2S (unaligned) Check: No unaligned support (0x01000024)
AXIMM2S (continuous) Midway:
BEATS: 0x00002000
CLOCKS: 0x00002000
COUNTS: 0x00002027
AXIMM2S (continuous) Midway:
STATUS: 0x30090000
BEATS: 0x00004000
CLOCKS: 0x000041e7
COUNTS: 0x00004218
AXIS2MM Check:
COUNTS: 0x00002135
ERR-CODE: 0
AXIS2MM (abort) Check:
COUNTS: 0x00000206
ERR-CODE: 0
Running AXI DMA test
Test has begin
AXIDMA Check:
%Error: %Error: Can't write 'logs/coverage.dat'
Aborting...
Aborted (core dumped)
`
Makefile not able to create log file and found the above error .kindly guide me for above issues.

thanks in advance

Hide OPT_SKIDBUFFER Declaration Unless FORMAL is Defined

Verilator v4.212 (and v4.202) fails with unconnected OPT_SKIDBUFFER
when FORMAL is undefined. I fixed this and pushed the change to
https://github.com/bobnewgard/axidmacheck (see Details below). The
diff is:

--- a/rtl/streamcounter.v
+++ b/rtl/streamcounter.v
@@ -58,7 +58,9 @@ module        streamcounter #(
                parameter       C_AXI_ADDR_WIDTH = 4,
                localparam      C_AXI_DATA_WIDTH = 32,
                parameter       C_AXIS_DATA_WIDTH = 32,
+`ifdef FORMAL
                parameter [0:0] OPT_SKIDBUFFER = 1'b1,
+`endif
                parameter [0:0] OPT_LOWPOWER = 0,
                localparam      ADDRLSB = $clog2(C_AXI_DATA_WIDTH)-3
                // }}}

Regards,
Bob Newgard

Details:

• ZipCPU/autofpga@f89d4dc
• bobnewgard@af7511a
• Verilator v4.212