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pipecnn

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

pipecnn_winograd

An OpenCL-Based FPGA Accelerator for Compressed YOLOv2

primesieve

🚀 Fast prime number generator

proteus

py_omen

Python version of the OMEN password cracker

pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

qiskit-terra

Qiskit is an open-source SDK for working with quantum computers at the level of extended quantum circuits, operators, and algorithms.

rfguess

基于机器学习的社工字典生成工具. A Machine Learning Approach for Password Guessing. The reproduction of (https://www.usenix.org/conference/usenixsecurity23/presentation/wang-ding-password-guessing)

rocket-chip

Rocket Chip Generator

sdaccel-tutorials

SDAccel Development Environment Tutorials

sdaccel_examples

SDAccel Examples

serv

SERV - The SErial RISC-V CPU

sm3_highp

A implement of Chinese SHA(SM3) on FPGA from SHU ACTION team

summer

tensorflow-1.4-billion-password-analysis

Deep Learning model to analyze a large corpus of clear text passwords.

turbopfor

Fastest Integer Compression

ultra-light-fast-generic-face-detector-1mb

💎 1MB轻量级人脸检测模型 (1MB lightweight face detection model)

vitis-ai

Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.

vitis_libraries

Vitis Libraries

vitis_with_100gbps_tcp-ip

100 Gbps TCP/IP stack for Vitis shells

vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

xcryptcore

Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)