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VU5P-based FPGA accelerator card development suite
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Interfaces available for each FPGA accelerator card are as follows:
One PCIe 3.0 x8
interfaceTwo DDR4
RDIMM interfacesTwo 100 Gbit/s
Ethernet interfaces
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PCIe features are as follows:
Two physical functions (PFs)
PF0
is for users. The size of Bar0 is 32 MB, and the size of Bar1 is 64 KB.PF1
is for management. The size of Bar0 space is 32 MB, and the size of Bar1 is 128 KB.
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Interface features between user logic and static logic are as follows:
- The data channel from user logic to static logic uses the AXI4-MM interface with a bit width of
512 bits
. - The control channel from user logic to static logic uses the AXI4-Lite interface with a bit width of
32 bits
.
- The data channel from user logic to static logic uses the AXI4-MM interface with a bit width of
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The DDR interface partition is as follows:
- Two DDR controllers are placed in the user logic partition.
- A maximum of two DDR controllers can be used.
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Based on the SDx 2017.4.op software platform and support for the development and design of the
C/C++/OpenCL
language. -
For details, see README.
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Interfaces available for each FPGA accelerator card are as follows:
One PCIe 3.0 x16
interfaceFour DDR4
RDIMM interfacesTwo 100 Gbit/s
Ethernet interfaces
-
PCIe features are as follows:
Two physical functions (PFs)
PF0
is for users. The size of Bar0 is 32 MB, and the size of Bar1 is 64 KB.PF1
is for management. The size of Bar0 space is 32 MB, and the size of Bar1 is 128 KB.
-
Interface features between user logic and static logic are as follows:
- The data channel from user logic to static logic uses the AXI4-MM interface with a bit width of
512 bits
. - The control channel from user logic to static logic uses the AXI4-Lite interface with a bit width of
32 bits
.
- The data channel from user logic to static logic uses the AXI4-MM interface with a bit width of
-
The DDR interface partition is as follows:
- Four DDR controllers are placed in the user logic partition.
- A maximum of four DDR controllers can be used.
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Provides FLASH CTRL, HWICAP CTRL, and IIC MASTER components and example projects.