Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel.

• RV32I 2.1
• Zifencei extension 2.0
• Zicsr extension 2.0
• M extension 2.0
• A extension 2.0
• C extension 2.0 (RV32 integer instructions)
• Machine-level ISA 1.11
• Supervisor-level ISA 1.11

Fuxi processor is designed for running GeeOS, or other simple operating systems or bare-metal software. Considering the complexity, the following functions has not yet been implemented:

• Memory privilege in mstatus register: MPRV bit and MXR bit are hardwired to 0.
• Virtualization support in mstatus register: TVM bit, TW bit and TSR bit are hardwired to 0.
• Physical Memory Protection: all PMP registers are hardwired to 0.

With default configuration (historical data, evaluated on Fuxi 0.0.1):

• Dhrystone 2.1: 0.60 DMIPS/MHz.
• CoreMark: 2.15 CoreMark/MHz.

The frontend fetches aligned 32-bit words, assembles mixed 16/32-bit instructions, and expands compressed instructions before the existing decoder. A four-entry instruction FIFO decouples fetch from decode; each entry retains its PC, prediction snapshot, raw instruction, and precise fetch-fault address. Both 16-bit and 32-bit instructions may start at a halfword boundary. Split-page instructions translate each page independently and report the faulting parcel in mtval/stval while keeping the instruction start in mepc/sepc.

Fuxi currently targets Chisel 7.13.0 and Scala 2.13.18. JDK 17 and sbt are recommended for building it; running the unit tests also requires Verilator.

By issuing the following command lines, you can get generated verilog file in directory verilog/build:

$ git clone https://github.com/MaxXSoft/Fuxi
$ cd Fuxi
$ make

See the test layout and support guide for directory organization and shared helpers.

All unit tests are available in directory src/test/scala. For example, unit test for decode stage is available in core/stages/DecoderTest.scala, you can run this test by executing the following command lines:

$ sbt
> Test / runMain core.stages.DecoderTest

CoreTest is an integration test provided in this repository, it can run simple RISC-V programs using the Fuxi core. We also provided some programs in directory src/test/resources. For example, you can run one of it:

$ sbt
> Test / runMain core.integration.CoreTest -if src/test/resources/fib.txt

Trace information during running program fib.txt will be printed to the console.

CoreTest supports the following command line arguments:

So you can test the core using a trace file generated by other processor or emulator:

> Test / runMain core.integration.CoreTest -if src/test/resources/fib.txt -tf src/test/resources/fib_trace.txt

For other details, please read the source file of CoreTest.scala.

All provided programs:

Copyright (C) 2020-2026 MaxXing. License GPLv3.

Special thanks to @Yukiteru Lee.