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pstr17r5b

使用DDS芯片AD9914产生线性扫频信号

pulp

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

python-interview

Python语言特性、网络、数据库、操作系统、算法知识点总结。

pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

qspiflash

A set of Wishbone Controlled SPI Flash Controllers

qwi00_led

qwi00_led is a simple LED control program.

raven-picorv32

Silicon-validated SoC implementation of the PicoSoc/PicoRV32

riffa

The RIFFA development repository

riscv

RISC-V CPU Core (RV32IM)

riscv-dv

Random instruction generator for RISC-V processor verification

riscv-fpu

Basic floating-point components for RISC-V processors

riscv-starship

Run rocket-chip on FPGA

riscv-vip

For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug

round_robin_arbiter

round robin arbiter

rsd

RSD: RISC-V Out-of-Order Superscalar Processor

rust_hdl

schoolmips

CPU microarchitecture, step by step

sdram-verification

This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed by Dinesh in Opencores.org

sdspi

SD-Card controller, using a SPI interface that is (optionally) shared

serial-studio

Multi-purpose serial data visualization & processing program

serv

SERV - The SErial RISC-V CPU

serv_soc

SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.

signal_generator_based_on_fpga

A very simple sine/AM/FM/ASK/FSK signal generator using DDS based on FPGA

simpletpu

A FPGA Based CNN accelerator, following Google's TPU V1.

skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

sm2_core

opensource crypto IP core

sm3_core

sm4_logic

sofa

SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA

spinalhdl

Scala based HDL