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I got repetitive issue, while doing @rw1nkler LiteX - Zephyr setup from his repository: https://github.com/antmicro-labs/2d-gpu/wiki/LiteX---Zephyr-tutorial

I'm using Ubuntu 18.04, so far I've installed all the prerequisites up to section: Prepare basic bit-stream, where I got stuck at command ./arty.py --with-ethernet. No matter what I tried to do, the reuslt was the same error:

ModuleNotFoundError: No module named 'liteiclink'

All the repositories were installed to the directory /home/kamil/Git/<repository_name>

My ~/.bashrc file looks following:

export PATH="${PATH}:/tools/Xilinx/Vivado/2019.2/bin"

export PYTHONPATH="${PYTHONPATH}:/home/kamil/Git/litex"
export PYTHONPATH="${PYTHONPATH}:/home/kamil/Git/litex-zephyr-build/third-party/migen"
export PYTHONPATH="${PYTHONPATH}:/home/kamil/Git/litex-zephyr-build/third-party/litedram"
export PYTHONPATH="${PYTHONPATH}:/home/kamil/Git/litex-zephyr-build/third-party/liteeth"
export PYTHONPATH="${PYTHONPATH}:/home/kamil/Git/litex-zephyr-build/third-party/liteiclink"
export PYTHONPATH="${PYTHONPATH}:/home/kamil/Git/litex-zephyr-build/third-party/litejesd204b"
export PYTHONPATH="${PYTHONPATH}:/home/kamil/Git/litex-zephyr-build/third-party/litepcie"
export PYTHONPATH="${PYTHONPATH}:/home/kamil/Git/litex-zephyr-build/third-party/litesata"
export PYTHONPATH="${PYTHONPATH}:/home/kamil/Git/litex-zephyr-build/third-party/litescope"
export PYTHONPATH="${PYTHONPATH}:/home/kamil/Git/litex-zephyr-build/third-party/litesdcard"
export PYTHONPATH="${PYTHONPATH}:/home/kamil/Git/litex-zephyr-build/third-party/litevideo"

We couldn't solve this problem together for a few weeks, although I triple checked all the prerequisites and consulted with my friends whether they got the same issue. I'd be grateful for any kind of help.

FastVDMA is available here https://github.com/antmicro/fastvdma

To integrate it with LiteX you have to generate Verilog code and wrap it in LiteX. Here is an example how a Verilog module can be wrapped: https://github.com/enjoy-digital/litesdcard/blob/master/litesdcard/emulator/linklayer.py#L109

I presume that to write the migen wrapper for the fastvdma we need to make it use the same internal bus as the LiteX - Wishbone. Even though the original code is really well-written there is no documentation whatsoever on connecting it to the Wishbone bus.
I had no problems with the Verilog generation for the default AXI4, but I have truly no idea how to configure it for Wishbone

As @rw1nkler suggested here we can use the LiteX module to translate between the AXI and Wishbone, but creating wrapper on top of a wrapper is never a good idea.

I wasn't quite sure where to create this issue, but let's keep everything in one place for now.

1. Go through Quick start guide from LiteX repo
2. Run LiteX on ArtyA7 board
3. Learn how LiteX attaches modules to Arty board (python script)
4. Arrange next meeting for further instructions

Task is to understand math behind blend operation on images and write program in python that performs blending of two images. Write some description in wiki board.

Resources:
https://en.wikipedia.org/wiki/Blend_modes
https://fstoppers.com/education/all-about-mathematics-blending-modes-382755

We need to setup some contribution rules. The ones proposed in the other project seem rather useful - CONTRIBUTING.md.

What I'd like to add to this:

• obligatory code formatting according to PEP8 and pylint. I'm not sure yet how this will work with the migen, but we'll see.
• I'd love to see some more articles on our wiki - if you find anything interesting regarding the project, please create the wiki page with your findings.

After discussion, I will open pull request with the CONTRIBUTING.md file.

1. Play with the fastVDMA test
2. Check out the DMATop.vcd waves in GTKWaves
3. Create our own tests(more images, different positions and configurations)
4. Describe results on our wiki

I have also created issue for @piotr-binkowski with request to update the documentation on CSR

Hey, could you add the rest of the team:
kacperchmiel97
kmezynski
alicjakwasny
piotrgrobelny
Apparently the mails sent by Piotr aren't getting delivered.

I have added links to useful resources to the project Wiki. Please, have a look at this.

1. Could we get remote access to PCs via SSH?

2. Where can we find tutorial you mentioned during our last meeting about ArtyA7 startup and programming procedure written by one of your workmates.

3. Do we need Vivado toolchain to programm ArtyA7 board? Unfortunately its size (~20GB) is problematic for our Linux with emulated disk.

4. When can we receive HDMI board extension for ArtyA7?

5. Which Linux distribution do you use for this project?

6. What are the functional requirements of our project? This is necessary for the report for our course.

you can start with https://github.com/enjoy-digital/litex