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Open FPGA tools

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CMake 0.62% C 0.09% C++ 49.86% Verilog 4.22% Rust 40.23% SystemVerilog 0.01% JavaScript 0.13% HTML 0.04% Coq 4.80%

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Support for multiple devices in gp4par

This issue is not about support for a specific device, only removing the assumption that we're targeting the SLG46620V.

PAR should always exit with the best solution found to date, rather than the current placement when the optimizer gave up

Support for vector top-level ports

Create framework for hardware-in-loop testing

Uninitialized read

Msan describes it well enough:

==12385==WARNING: MemorySanitizer: use-of-uninitialized-value
    #0 0x8b2c55 in Greenpak4BitstreamEntity::GetNetlistEntity() /home/whitequark/Work/openfpga/build/../src/greenpak4/Greenpak4BitstreamEntity.cpp:98:5
    #1 0xc3d20f in Greenpak4PGA::Save(bool*) /home/whitequark/Work/openfpga/build/../src/greenpak4/Greenpak4PGA.cpp:293:51
    #2 0xa61224 in Greenpak4Device::WriteToFile(std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >) /home/whitequark/Work/openfpga/build/../src/greenpak4/Greenpak4Device.cpp:578:7
    #3 0x4df9b4 in main /home/whitequark/Work/openfpga/build/../src/gp4par/main.cpp:230:2
    #4 0x7fd6a5f7a5ef in __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x205ef)
    #5 0x43ee18 in _start (/home/whitequark/Work/openfpga/build/bin/gp4par+0x43ee18)

  Uninitialized value was stored to memory at
    #0 0x8b2bb7 in Greenpak4BitstreamEntity::GetNetlistEntity() /home/whitequark/Work/openfpga/build/../src/greenpak4/Greenpak4BitstreamEntity.cpp:97:16
    #1 0xc3d20f in Greenpak4PGA::Save(bool*) /home/whitequark/Work/openfpga/build/../src/greenpak4/Greenpak4PGA.cpp:293:51
    #2 0xa61224 in Greenpak4Device::WriteToFile(std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >) /home/whitequark/Work/openfpga/build/../src/greenpak4/Greenpak4Device.cpp:578:7
    #3 0x4df9b4 in main /home/whitequark/Work/openfpga/build/../src/gp4par/main.cpp:230:2
    #4 0x7fd6a5f7a5ef in __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x205ef)

  Uninitialized value was created by a heap deallocation
    #0 0x4ac414 in operator delete[](void*) (/home/whitequark/Work/openfpga/build/bin/gp4par+0x4ac414)
    #1 0xf15187 in PARGraphNode::~PARGraphNode() /home/whitequark/Work/openfpga/build/../src/xbpar/PARGraphNode.cpp:32:1
    #2 0xed5668 in PARGraph::~PARGraph() /home/whitequark/Work/openfpga/build/../src/xbpar/PARGraph.cpp:33:3
    #3 0xed6a33 in PARGraph::~PARGraph() /home/whitequark/Work/openfpga/build/../src/xbpar/PARGraph.cpp:31:1
    #4 0x6db09e in DoPAR(Greenpak4Netlist*, Greenpak4Device*) /home/whitequark/Work/openfpga/build/../src/gp4par/par_main.cpp:62:2
    #5 0x4deb14 in main /home/whitequark/Work/openfpga/build/../src/gp4par/main.cpp:225:6
    #6 0x7fd6a5f7a5ef in __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x205ef)

Logic loop cannot be synthesized

Source: http://hastebin.com/akuliheciw.v (use yosys -p "synth_greenpak4 -json loop.json" loop.v).
As-is, gp4par will silently remove the loop and make a design where the inverter's IN is not connected.

Timing-driven placement

Rather than seeking to minimize cross-connections, try to minimize critical path delays. Using a cross connection will of course add delay.

This requires a timing engine (see #39 ).

Module-related bug

When compiling this file:

module ClkDiv #(parameter DIVISOR = 1) (clk, clkdiv);

  input  wire                     clk;
  output reg  [$clog2(DIVISOR):0] clkdiv = DIVISOR;

  always @(posedge clk)
    if(clkdiv == 0)
      clkdiv <= DIVISOR;
    else
      clkdiv <= clkdiv - 1;

endmodule

module Blinky(o_led1);

  (* LOC="P3" *) output wire o_led1;

  GP_LFOSC #(
    .AUTO_PWRDN(0),
    .OUT_DIV(16)
  ) lfosc (
    .CLKOUT(clk)
  );

  ClkDiv #(
    .DIVISOR(108*3)
  ) clkdiv1 (
    .clk(clk),
    .clkdiv(clkdiv_state)
  );

  assign o_led1 = (clkdiv_state == 0);

endmodule

as recommended:

all: Blinky.txt

clean:
    rm -f Blinky.txt

%.json: %.v
    yosys -p 'read_verilog $<; synth_greenpak4 -top $* -part SLG46620V -json $@'

%.txt: %.json
    gp4par $< --top $* --output $@ --unused-pull down

the following error, and nothing else, is shown:

ERROR: Attempted redeclaration of net attribute "src"

which disappears if I inline the ClkDiv module.

Support for Yosys' -q/-l/-L options

I.e. to make it possible to write everything to the log, and nothing except warnings/errors to the console. This is quite convenient to reduce the amount of noise, especially with editor buildsystem integration.

Also would be great if you flushed stdout before writing to stderr, since right now the errors are placed before the starting banner when running gp4par through Sublime Text's buildsystem integration (I think it uses pipes?)

$assert cells should be ignored during synthesis

Currently the SystemVerilog assert property (...); causes this PAR error:

ERROR: Cell "$techmap\core.$assert$foo.v:61$28" is of type "$assert" which is not a valid GreenPak4 primitive

I think they should be removed. But I'm not sure at what stage, since, assuming it reaches PAR, it probably drags some synthesized logic with it, so maybe yosys should do that?

Support for PGEN mode of LUT4/PGEN block

Need to take care of #25 first

Implement post-PAR timing analysis

Static is preferred, topological would be OK probably. Needs timing data that is not currently released by Silego. Will need to characterize or get them to publish it.

Add Verilog-AMS sim models for analog hard IP

Support for latch mode of GP_DFF cells (separate primitive GP_DLATCH?)

Allow GP_DFF cells to be placed in unused GP_SHREG sites

GP_SHREG PAR bug

Repro:
Shreg.json.txt
Shreg.bit.txt

As can be seen together with the reference yosys diagram below:

OUTB of GP_SHREG$267 should be connected to IN1 of GP_3LUT$263, which further feeds back into IN of GP_SHREG$266. If you open the bitstream in the GP4 vendor tool, it is clear that OUTB is not connected anywhere. Instead, IN1 of GP_3LUT$263 as well as p4_o are connected to OUTA.

Synchronize defaults with Yosys models

Currently, GP_RCOSC and friends have .AUTO_PWRDN parameter default to 1 in Yosys (which is the sane behavior) and to 0 in gp4par (which is a footgun I've wasted quite some time at). gp4par should use proper defaults.

This is related but not same as #5 (and that one is an improvement, this is a bug).

Fix remaining non-truly-fatal LogFatals in gp4par

Support supplying gp4par options --unused-drive, --unused-pull via toplevel module attributes

Support for SLG46140

Allow placing GP_INV in GP_LUT sites

Seriously. This annoys me every time I'm inverting something.

Use a RNG independent of machine, OS, endianness, etc

Instead of libc rand().

Create framework for co-simulation test cases that compare hardware-in-loop behavior to iverilog simulation

Support for SPI slave block

This will need some tweaking since it disables a lot of resources in one switch matrix. This may require deleting the duals from some blocks (oscillators etc)

GP_RCOSC.OSC_FREQ does not work

module top((* LOC="P5" *) output q);
    GP_RCOSC #( 
        .AUTO_PWRDN(1'b0),
        .OSC_FREQ("2M")
    ) rcosc (
        .CLKOUT_FABRIC(q)
    );
endmodule

Still outputs at 20k.

Detect bitwidth mismatches in linting

Assignments with mismatched widths.

Assignments of numbers without specified width (defaults to 32 bits) when the destination is wider than 32 bits. Been bit by this...

wire [63:0] = 12345

The 12345 is assumed to be 32 bits wide.

Cool idea, BTW. Good luck with the project.

C++11 required for build

I get the following error when trying to build:

/home/clifford/Temp/openfpga/src/greenpak4/Greenpak4Device.cpp: In destructor ‘virtual Greenpak4Device::~Greenpak4Device()’:
/home/clifford/Temp/openfpga/src/greenpak4/Greenpak4Device.cpp:44:11: error: ‘x’ does not name a type
  for(auto x : m_bitstuff)
           ^
...

Adding the following line to src/greenpak4/CMakeLists.txt fixed the issue:

set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -std=c++11")

I'm not a CMake expert. I'm sure there is a better way to do this.

    wire [5:0] phases;
    always @(*) begin
        phases <= 6'b000000;
        case(state)
            0: phases <= 6'b100100;
            1: phases <= 6'b001001;
            2: phases <= 6'b010010;
            3: phases <= 6'b011000;
            4: phases <= 6'b000110;
            5: phases <= 6'b100001;
        endcase
    end

    assign {p1h} = phases;

3pdrive.json.txt

INTERNAL ERROR: tried to assign node to illegal site

To reproduce:

module ClkDiv #(parameter DIVISOR = 1) (clk, clkdiv);

  input  wire                     clk;
  output reg  [$clog2(DIVISOR):0] clkdiv = DIVISOR;

  always @(posedge clk)
    if(clkdiv == 0)
      clkdiv <= DIVISOR;
    else
      clkdiv <= clkdiv - 1;

endmodule

module Blinky(o_led1);

  (* LOC="P3" *) output wire o_led1;

  GP_LFOSC #(
    .AUTO_PWRDN(0),
    .OUT_DIV(16)
  ) lfosc (
    .CLKOUT(clk)
  );

  ClkDiv #(
    .DIVISOR(108*3)
  ) clkdiv1 (
    .clk(clk),
    .clkdiv(clkdiv_state)
  );

  reg blink;
  always @(posedge clk)
    if(clkdiv_state == 0)
      blink <= ~blink;

  assign o_led1 = (blink == 0);

endmodule

and apply the workaround from #7.

module ClkDiv #(parameter DIVISOR = 1) (clk, clkdiv);

  input  wire                     clk;
  output reg  [$clog2(DIVISOR):0] clkdiv = DIVISOR;

  always @(posedge clk)
    if(clkdiv == 0)
      clkdiv <= DIVISOR;
    else
      clkdiv <= clkdiv - 1;

endmodule

module Blinky(o_led1, o_led2, o_led3);

  (* LOC="P3" *) output wire o_led1;
  (* LOC="P4" *) output wire o_led2;
  (* LOC="P5" *) output wire o_led3;

  wire clk;
  GP_LFOSC #(
    .AUTO_PWRDN(0),
    .OUT_DIV(16)
  ) lfosc (
    .CLKOUT(clk)
  );

  wire clkdiv_state;
  ClkDiv #(
    .DIVISOR(108*3)
  ) clkdiv1 (
    .clk(clk),
    .clkdiv(clkdiv_state)
  );

  localparam RED = 0, REDYELLOW = 1, YELLOW = 2, GREEN = 3, GREENBLINK = 4;
  reg[2:0] state;
  always @(posedge clk)
    if(clkdiv_state == 0)
      case(state)
        RED:
          state <= REDYELLOW;
        REDYELLOW:
          state <= YELLOW;
        YELLOW:
          state <= GREEN;
        GREEN:
          state <= GREENBLINK;
        GREENBLINK:
          state <= RED;
      endcase

  wire clkdiv_blink;
  ClkDiv #(
    .DIVISOR(108/2)
  ) clkdiv2 (
    .clk(clk),
    .clkdiv(clkdiv_blink)
  );

  reg blink;
  always @(posedge clk)
    if(clkdiv_blink == 0)
      blink <= ~blink;

  wire[2:0] leds;
  always @(posedge clk)
    case(state)
      RED:
        leds = 3'b001;
      REDYELLOW:
        leds = 3'b011;
      YELLOW:
        leds = 3'b010;
      GREEN:
        leds = 3'b100;
      GREENBLINK:
        if(blink == 0)
          leds = 3'b000;
        else
          leds = 3'b100;
    endcase

  assign {o_led1, o_led2, o_led3} = leds;

endmodule

and apply the workaround from #7.

GP_BANDGAP: AUTO_PWRDN=0, CHOPPER_EN=1
GP_COUNT{8,14}: CLKIN_DIVIDE=1 (assuming that's always valid)
GP_LFOSC: AUTO_PWRDN=0, PWRDN_EN=0
GP_{RINGOSC,RCOSC}: AUTO_PWRDN=0, PWRDN_EN=0, PRE_DIV=1, FABRIC_DIV=1

All other ones should result in a DRC error if not specified.

logtools update broke gp4prog --debug

It looks something like this now, when within LogIndenter:

    H→D:     01    _    25    _    07    _    00    _    14    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    
    D→H:     01    _    25    _    3f    _    00    _    14    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00    00

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