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Neuromorphic architectures are hardware architectures that use the biologically inspired neural functions as the basis of operation. Information processing based on spiking neuron architectures have caught considerable attention in recent years due to its low power consumption compared to traditional artificial neural networks. In this project, as the first stage, we are implementing parallel multiple processing elements based on RISC-V architecture to represent biological neurons. Single neurons can be implemented as a single processor with local memory access or since the spike time of biological neurons is in the millisecond order multiple neurons can be virtualized to a single processor. At the second stage of the process, we are expecting to design encoders and decoders to benchmark the architecture by solving classical machine learning problems.

Home Page: https://cepdnaclk.github.io/e16-4yp-neuromorphic-architecture/

Verilog 1.63% HTML 0.28% Standard ML 0.01% VHDL 96.79% Mathematica 0.01% Python 0.01% Assembly 0.08% SystemVerilog 0.37% Tcl 0.01% SuperCollider 0.06% C 0.63% C++ 0.01% Makefile 0.13% Shell 0.01% GDB 0.01% Scheme 0.01% SAS 0.01%
fpga neuromorphic-computing neuromorphic-engineering neuromorphic-hardware risc-v

e16-4yp-neuromorphic-architecture's Introduction

Neuromorphic Architecture

Neuromorphic architectures are hardware architectures that use the biologically inspired neural functions as the basis of operation. Information processing based on spiking neuron architectures have caught considerable attention in recent years due to its low power consumption compared to traditional artificial neural networks.

In this project, as the first stage, we are implementing parallel multiple processing elements based on RISC-V architecture to represent biological neurons. Single neurons can be implemented as a single processor with local memory access or since the spike time of biological neurons is in the millisecond order multiple neurons can be virtualized to a single processor. At the second stage of the process, we are expecting to design encoders and decoders to benchmark the architecture by solving classical machine learning problems.

Team

Supervisors

  • Dr. Isuru Navinna, email
  • Dr. Mahanama wickramasinghe, email
  • Prof. Roshan G. Ragel, email
  • Dr. D.M.I.S. Dasanayake, email

External Links

e16-4yp-neuromorphic-architecture's People

Contributors

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