RV-PC is a GUI-capable RISC-V computer system on low-end FPGA boards. It is based on RVSoC, a portable and Linux capable RISC-V computer system on an FPGA. Currently, only the Digilent Nexys4 DDR and the Nexys A7 board is supported.
Demo: https://youtu.be/Kt_iXVAjXcQ
- RV32IMA instruction set
- 5-stage pipelined processor core
- Sv32 MMU
- L0 instruction/data caches and the shared L1 cache
- Linux / X Window System support
- 100Mbps Ethernet / VGA display / microSD card/ USB mouse / PS2 keyboard support
Recommended environment: Ubuntu 18.04 LTS
1. Copy the disk image file(initmem.bin) to the microSD card.
Warning: This can potentially cause data loss. Please do this at your own risk.
$ dd if=initmem.bin of=/dev/[Device file name of your SD card]
2.Insert the microSD card into the FPGA board, and connect a USB mouse, VGA display, PS/2 keyboard and (optionally) an Ethernet cable to the FPGA board.
Connect the USB mouse to the built-in USB connector on the board. PS/2 keyboards can be connected to the board by inserting a Pmod PS2 into the lower part of the Pmod JB port. The default resolution of the display is 640x480.
You can create a Vivado project with the following command
$ vivado -mode batch -source main.tcl
or by selecting main.tcl in Tools -> Run Tcl Script in Vivado GUI.
Then open main/main.xpr with Vivado.
You can also use the pre-built m_main.bit.
If you use RV-PC by connecting it to a host PC, you can perform JTAG configuration. If the RV-PC is to be used standalone, you have to perform Quad-SPI configuration.
The method of building the disk image file is almost the same as the one for RVSoC.
The only differences are:
- Instead of rvsoc_patch.zip, devicetree_104mhz.zip and initmem_gen.zip, use the corresponding directories in diskimage/ in this repository.
- Change the BBL configure option from --with-arch=rv32imac to --with-arch=rv32ima
You can use diskimage/run.sh.
RV-PC is released under the MIT License, see LICENSE.txt.
RVSoC,
a portable and Linux capable RISC-V computer system on an FPGA
RVCore,
an optimized RISC-V soft processor of five-stage pipelining