dpretet / friscv

RISCV CPU implementation in SystemVerilog

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Overview

FRISCV is a SystemVerilog implementation of the RISCV ISA:

• Built around a 3-stage pipeline
• In-order execution
• AXI4-lite for instruction and data bus
• Instruction & data cache units
• Privilege modes:
  • Machine-mode only for simple embedded system
  • User-mode for secure embedded system
• Physical memory protection (PMP) & Physical Memory Attribute (PMA), up to 16 regions
• External, software and timer interrupts
• Support multiple (optional) extensions:
  • RV32I & RV32E architecture
  • Zifencei
  • Zicsr
  • Zicntr
  • Zihpm
  • M extension (multiply/divide)
  • Clint extension

The core is compliant with the official RISCV testsuite.

Architecture

The IP is decribed in two layers:

• the core, a RISCV hart to execute an assembler program
• the platform, instantiating a hart, an AXI4 crossbar and the peripherals

The core is compact and composed by:

• the control unit, fetching and sequencing the instructions
• the processing unit, executing the arithmetic and memory access instructions
• the cache units, one for instruction, one for data bus
• the CSR unit
• the ISA registers
• the memory protection unit for less-privilege mode memory access

More details of the architecture can be found in the:

• Architecture chapter.
• IOs and parameters chapter

Verification environment

The core is verified with several testsuites, present in test folder:

• White-Box Assembler testsuite
• Privilege / Security testsuite
• RISCV Compliance testsuite
• C testsuite
• Apps testsuite
• SV testsuite

The flow relies on:

• Icarus Verilog 11
• Verilator 4.2
• SVUT
• RISCV toolchain

Performance

Coremark has been performed on the platform (core with caches + AXI interconnect and peripherals). The IP demonstrates 2.87 coremark / MHz:

CoreMark 1.0 : 1435 / GCC 11.1.1 -O1

Synthesis & Area

The core is usually synthesized with Yosys during continuous integration. to ensure. Follows area figured out by a synthesis with Vivado 2021.2:

Core:

• Slice LUTs: 13635
• Slice registers: 2774
• RAMs: 0
• DSPs: 0

Platform:

• Slice LUTs: 16032
• Slice registers: 4889
• RAMs: 0
• DSPs: 0

Validation environment

The core has not been yet tested on hardware, but a synthesis flow based in Yosys is available in syn folder.

Development plan

• HW development plan
• SW development plan

License

This IP core is licensed under MIT license. It grants nearly all rights to use, modify and distribute these sources.

However, consider to contribute and provide updates to this core if you add feature and fix, would be greatly appreciated :)

friscv's Issues

Support Concurrent read/write access

This branch contains updates in memfy and dcache to support concurrent read/write access if no address collision can occur. The updates are the following:

• memfy: AXI_ORDERING parameter set to 1 generate another circuit to detect the r/w collisions. Look-up tables (LUT) for read and write channels are instantiated to track ongoing requests. AXI_ORDERING=0 follows the previous behaviour, read and write requests can't be issued in parallel. Outstanding read blocks write requests, and vice & versa.
• dcache pusher: cache write is slightly different, all write needing to update the blocks are packed into a FIFO, emptied once no new write request are issued by memfy. Before this update, read and write were fully parallel.
• cache blocks: architecture evolved, now having two fully independent port, once for read data path (fetcher), once for write data path (pusher). A port makes write passing before read. Before this update, port 1 was read-only, port 2 write-only.

The branch is not yet merged because two problems encountered during debug, that can't be identified clearly neither understood for the moment:

• wba-testsuite / core configuration: at some point, memfy generates a log indicating too many write completions have been issued by the dcache. True for both icarus and verilator
• apps/repl: the benchmark command issued a load_misaligned exception.