dwarning / va-models

Verilog-A simulation models

Verilog-A Models for Circuit Simulation

This repository is a collection of compact models written in Verilog-A with the purpose of simulation of state-of-the-art electronic circuits.

The models covering a wide range of devices :

• MOS with different flavours like SOI, FinFET and bulk processes
• HV-MOS like hisim_hv
• BJT like HICUM, MEXTRAM and VBIC
• HEMT like ASMHEMT, mvsg_cmc
• IGBT the well known Hefner model in Verilog-A
• Passive devices like diodes, varactors and non-linear resistors
• Sensors

Actual version status:

Model	Version	Model	Version
Resistor		MG MOSFET
r2_cmc	1.0.1	bsim-img	102.9.6
r3_cmc	1.1.1	bsim-cmg	111.2.1
Diode		HV-MOS
diode_cmc	2.0.0	hisim_hv	2.5.1
juncap	200.6.1	psphv	1.0.6
Varactor		BJT
mosvar	1.3.0	hicum0	2.1.0
MOSFET		hicum2	3.0.0
bsim4	4.8.0	mextram	505.4.0
bsim6	6.1.1	vbic	1.3
bsimbulk	107.1.0	fbh_hbt	2.3
ekv26	2.6	HEMT
ekv3	302.00	angelov	2.0
hisim2	3.2.0	angelov_gan	2.0
psp102	102.5.0	asmhemt	101.4.0
psp103	103.8.2	epfl-hemt	3.0.0
psp104	104.0.0	mvsg_cmc	3.2.0
SOI MOSFET		IGBT
l-lutsoi	102.7.0	igbt3	1.0.0
bsim-soi	4.6.1
hisim-soi	1.5.0
hisim-sotb	1.3.0

All models are checked for syntax belong Verilog-AMS Language Reference Manual Version 2.4.0. https://accellera.org/downloads/standards/v-ams The models are modified mostly for convergence improvements. Equations are untouched. So few parameter limits are changed to prevent division by zero and especially bipolar models lacks suitable limit function to prevent divergence in Newton-Raphson iteration process. Changes are noticed in Changelog.

At the moment this code modifications are adapted to NGSPICE and Xyce simulators. But in future the code can adapted to the requirements and restrictions of other simulators e.g. Qucs etc.

Any code directory has a set of test cases to show main functionality and performance of the models. Contributions for more practical use cases are welcome.

Related Projects

The usage of the model code is mainly dependent from following projects: OpenVAF, NGSPICE, ADMS and Xyce.

OpenVAF

OpenVAF can be build as a standalone CLI program that can compile Verilog-A files to shared objects that comply with the simulator independent OSDI interface.

Detailed documentation, examples and precompiled binaries of all release are available on the website. To test the latest development version you can download nightly version of OpenVAF for linux here.

OpenVAF has been tested with NGSPICE version 39. It can already support a large variety of compact models.

Furthermore, some Verilog-A language features are currently not supported by openVAF:

• Laplace transform filters
• Language constructs: $abstime(), @cross()
• Indirect branch contribution
• Paramset definition

NGSPICE

NGSPICE is a open source simulator for electronic circuit simulation. Source code, examples and precompiled binaries of all release are available on the website.

NGSPICE is stable and in an regulary update process.

Xyce

Xyce is a open source simulator for electronic circuit simulation. Source code, documentation and precompiled binaries of all release are available on the website.

Xyce is stable and in an regulary update process. ADMS/Xyce is supporting small signal noise analysis.

How to build the models

NGSPICE

Download OpenVAF (Linux or Windows) from https://openvaf.semimod.de/download/ and place the executable here in the PATH.

Linux:

cd code
openvaf-compile-va.sh for Linux

Windows:

cd code
openvaf-compile-va.bat for MS Windows

Xyce

Xyce must be installed and their executables in the PATH. These days only Linux executables with the ability to load shared libraries are available. Another prerequisite is the availability of ADMS. ADMS source code may be downloaded from the Qucs/ADMS GitHub project website .

A user guide for Verilog-A models for Xyce can be found under the website .

Linux:

cd code
adms-compile-va.sh for Linux

Windows:

cd code
adms-compile-va.bat for MS Windows

Binary packages

Released are pre-compiled models for linux (Ubuntu 22.04 checked) and Windows 10 (64bit) ready for usage with osdi configured ngspice version > 39.

Project structure

VA-Models

• admslibs The place where the binaries reside after execution the adms-compile script
• code Below this folder all the VA models reside
• examples
  • ngspice ngspice example scripts
  • Qucs-S qucs-s example schematics
  • Xyce Xyce example scripts
• memory_test Script for memory check (Linux only), only for debugging purpose
• osdilibs The place where the binaries reside after execution the osdi-compile script

General Usage Instructions NGSPICE

Copy the .osdi files from directory osdilibs to the place where the NGSPICE code models (.cm) are located, e.g. /usr/local/share/ngspice/osdi (linux), C:\Spice64\lib\ngspice (Windows).

Other way (as shown in the example files) is the load command pre_osdi ../../osdilibs/bsimcmg.osdi in the NGSPICE control section. You can also extend the ngspice environment variable SPICE_LIB_DIR to your_path/code/osdilibs

It is important that the .model card use the name of the Verilog-A module, e.g. in case of bsimcmg: .model BSIMCMG_N bsimcmg_va.

Edit file 'spinit', typically found in share/ngspice/scripts: To enable OSDI usage comment out the line

'unset osdi_enabled'

General Usage Instructions Xyce

General instruction to build shared library from Verilog-A source with the Xyce provided tool buildxyceplugin:

buildxyceplugin -o ekv26 -d ekv26.va ..

Copy the .so files from directory admslibs to your working directory.

This ekv example will use the compiled shared library and simulate the simple MOS amplifier circuit file:

Xyce -plugin ekv26.so mosamp2.cir

The results are written into ASCII file and can plotted with gnuplot in persist mode:

gnuplot -p mosamp2.plt

General Usage Instructions Qucs-S

For several models Qucs-S example schematics are provided. Because qucs-s doesn't support loading osdi shared libs with relative pathes in schematics "Nutmeg script" the user have to edit the local .spiceinit file for ngspice and add the load command for the wanted osdi model, e.g. for linux (perhaps under $HOME):

osdi ~/Projects/spice/Verilog-A/VA-Models/osdilibs/ekv3.osdi

Windows (perhaps under C:\Users<User name>):

osdi C:\Projects\spice\Verilog-A\VA-Models\osdilibs\ekv3.osdi

Acknowledgement

The team of openVAF developer from Semimod GmbH https://semimod.de/ .

The NGSPICE development team https://ngspice.sourceforge.io/ .

The Xyce development team https://xyce.sandia.gov/ .

Geoffrey Coram for his excellent tool VAMPyRE https://github.com/analogdevicesinc/vampyre .

And last but not least: All the model authors for their elaborate and complex work.

Copyright

Copyright of various owners, see individual code directories.

Most model codes are licensed under the Educational Community License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.osedu.org/licenses/ECL-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

va-models's Issues

openvaf compilation failures

I have several of the models that don't compile with openvaf due to the __XYCE__ check present in the code. I am using latest openvaf version 23.5.0 downloaded precompiled from the website. I compile the modules using the openvaf-compile-va.sh script in the code directory.
Errors for hicum2/vacode/hicumL2V3p0p0.va:

error: macro '`elsif' has not been declared
    --> /home/verhaegs/eda/code/VA-Models/code/hicum2/vacode/hicumL2V3p0p0.va:818:1
    |
818 | `elsif __XYCE__
    | ^^^^^^ macro not found here

error: unexpected token identifier; expected ';'
    --> /home/verhaegs/eda/code/VA-Models/code/hicum2/vacode/hicumL2V3p0p0.va:819:5
    |
818 | `elsif __XYCE__
    |                - expected ';'
819 |     Vbiei = $limit(V(br_biei),"typedpnjlim_new",VT,VT*ln(VT/(`M_SQRT2*ibeis_t)));
    |     ^^^^^ unexpected token

error: '__XYCE__' was not found in the current scope
    --> /home/verhaegs/eda/code/VA-Models/code/hicum2/vacode/hicumL2V3p0p0.va:818:8
    |
818 | `elsif __XYCE__
    |        ^^^^^^^^ not found

error: could not compile `hicumL2V3p0p0.va` due to 3 previous errors

This happens for the following models:

• hicum2/vacode/hicumL2V3p0p0.va
• IGBT/vacode/nigbt.va
• mextram/505p2p0_vacode/bjt505.va
• mextram/505p2p0_vacode/bjt505t.va
• vbic/vacode/vbic_1p3.va

I now compiled the code by commenting out the `elsif __XYCE__ sections.

bug in bsim4.va

There is a bug ... in bsim4.va, lines 12356 and 12357.

These statements effectively disconnect di,d and si,s if BSIM4rdsMod is not set.
Otherwise they seem correct, and they should be made conditional on BSIM4rdsMod.

Greetings
felix

bsim4 again

During refactoring, the default for ni0sub has changed from 1.45e10 to 1.45e16. I wonder if this was intentional. Further down, in code conditional on mtrlmod==0, the constant 1.45e10 is still used in ni. I had a cursory look at the original model, and it looks like 10 there as well.

Within the five contribution statements I(..) <+ BSIM4type * ddt(..), replacing BSIM4type by just type will simplify optimisation: both are supposedly constant, but BSIM4type is harder to tell. Generally, perhaps it will be better to get rid of all/most BSIM4* variables in favour of actual (local)param constants?

Related, the @(initial_step) event kludge looks wrong, and appears to make things worse. Perhaps it should be made conditional, as in

   `ifdef insideADMS
     `define INITIAL_INSTANCE @(initial_instance)
   `elsif __SOME_SOFTWARE__
     `define INITIAL_INSTANCE @(initial_step)
   `else
      `define INITIAL_INSTANCE
   `endif

Thanks
felix

bsim4 should use $param_given

All the parameters in bsim4.va are declared with a default value of NOT_GIVEN (or INT_NOT_GIVEN), which I suppose is done in order to set the "Given" variables like
BSIM4scGiven = (BSIM4sc == `NOT_GIVEN) ? 0 : 1;
However, Verilog-A has had the $param_given() function for almost 20 years now. Please use that. It should be more efficient, and simulators will show the correct values when playing back model parameters.

Also, note that default values can depend on other parameters, so:
if (!BSIM4aigsGiven)
BSIM4aigs = (BSIM4type == NMOS) ? 1.36e-2 : 9.80e-3; can be handled in the parameter declaration: parameter real aigs = (type == NMOS) ? 1.36e-2 : 9.80e-3;

model adaptations, question

The README states that models are "adapted" to specific implementations. I wonder what these adaptations are and if they could be made conditional for where they seem to be useful.

Some model generators hardwire preprocessor constants, such as `insideADMS, to protect non-ADMS users by making changes conditional on such constants.

Could this practice please be considered (or documented) for other backends as well? This will increase the usefulness of the endeavour, and will make changes easier to spot.

Greetings
felix

license issue

According to [1], the bsim4.va file is under CC-BY-NC 4.0. This note is omitted in the file header, unfortunately. However, if they mean it, commercial use of this code is prohibited.

Please state the license more clearly. For commercial purposes, the original C code seems to be a better choice.

[1] https://github.com/cogenda/VA-BSIM48/blob/master/README.md

VA implementation of Angelov/Angelov GaN

Hello! Is it possible to add Verilog-A implementations of Angelov and Angelov GaN models to the repo?