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iso14229

ISO 14229 (UDS) server and client for embedded systems

k-ar

Autosar BSW modules.

k-ar-1

AUTOSAR Layer for my other projects.

k-os

An OSEK-VDX implementation.

linux

Linux kernel source tree

linux-4.19

linux-on-litex-vexriscv

Linux on LiteX-VexRiscv

liteapp

LiteApp is a high performance mobile cross-platform implementation, The realization of cross-platform functionality is base on webview and provides different ideas and solutions for improve webview performance.

mini-dso

用STC单片机制作的简易示波器 / DIY Mini Digital Storage Oscilloscopes(DSO) with STC MCU

mips-cpu

Verilog implementation of a subset of MIPS 32 Bit Processor Instructions, ISA design, Assembler Design and Compiler design

mips-cpu-1

MIPS CPU implemented in Verilog

mips-cpu-2

A verilog implementation of MIPS ISA.

mips-processor

A crude and simple (but working!) MIPS processor, written in Verilog and designed for implementation on a DE/2 board (Cyclone II FPGA)

mips-processor-verilog

mkdocs

Project documentation with Markdown.

mpeg2fpga

An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.

neorv32

A small and customizable full-scale rv32imacbuZicsr_Zifencei RISC-V CPU and SoC written in platform-independent VHDL.

openmips

A full implementation of the MIPS32 Release 1 ISA, including virtual memory, TLB, instruction and data caches, interrupts and exceptions, over 100 hw/sw tests, and full ISA compliance

openwrt-allwinner-chip-with-nand

This repository is a mirror of https://git.openwrt.org/openwrt/openwrt.git It is for reference only and is not active for check-ins or for reporting issues. We will continue to accept Pull Requests here. They will be merged via staging trees then into openwrt.git. All issues should be reported at: https://bugs.openwrt.org

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

python-can-isotp

A Python package that provides support for ISO-TP (ISO-15765) protocol

python-udsoncan

Python implementation of UDS (ISO-14229) standard.

riscv

RISC-V CPU Core (RV32IM)

riscv-1

Verilog implementation of a RISC-V core

riscv-dbg

RISC-V Debug Support for our PULP RISC-V Cores

riscv-soc-cores

riscv64-nommu-buildroot

rocket-chip

Rocket Chip Generator

rudolv

RISC-V processor

simple-usb-oscilloscope-pcb