efabless / ef_tcc32

A 32-bit Timer/Counter/Capture Soft IP (Verilog)

EF_TCC32

A 32-bit Timer/Counter/Capture Soft IP in Verilog HDL. It has a generic bus interface compatible with wrapper_gen.py. Three bus wrappers are provided for: AHB-Lite, APB and WB.

Features

• Up/Down Counting
• One Shot or Periodic Timer
• External Events Capturing/Counting
• 8-bit Clock Prescaler (Timer only)
• 3 Interrupt sources
  • Timer Time-out
  • Counter Match
  • Event Capture

The Interface

EF_TCC32

Port name	Direction	Type	Description
clk	input		Clock
rst_n	input		Active low reset
ctr_in	input		External events input
period	input	[31:0]	32-bit Timer Period
ctr_match	input	[31:0]	32-bit match value (counter mode)
tmr	output	[31:0]	Current timer value
cp_count	output	[31:0]	Current counter value
clk_src	input	[3:0]	clk source (9: ctr_in, 8: clk, 0-7: clk/2 to clk/256)
to_flag	output		Time out flag
match_flag	output		Match flag
tmr_en	input		Timer enable
one_shot	input		One Shot mode enable (default: periodic)
up	input		Up counting enable (default: down counting)
cp_en	input		External events capturing enable
cp_event	input	[1:0]	External Event type (1: posedge, 2: negedge, 3: both)
cp_flag	output		Capture event received flag
en	input		Global enable

EF_TMR32 Internals

Modes of Operation

mode	tmr_en	cp_en	clk_src	description
Timer	1	0	0-8	Counts clock cycles to keep track of time. - clk_src 8: clk, 0-7: clk/2 to clk/256 - up: 0: down counting (period to 0), 1: up counting (0 to period) - one_shot: 0:periodic, 1:one shot - period: starting/terminal count for down/up counting. - to_flag: is set when the tmr reaches the terminal count (up:period, down:0)
Counter	1	0	9	Similar to the Timer but it counts external pulses coming on ctr_in. match_flag is set when tmr matches ctr_match. The counting can be up/down and to/from period register
Event Capture	1	1	0-8	Capture the time between two events on ctr_in. cp_event sets the event: 1:Raising Edge, 2:Falling Edge or 3:Both. cp_flag is set when two two consecutive events are observed; once set, cp_count shows the current count.

I/O Registers

Timer Value Register [offset: 0x00, RO]

Timer Period Register [offset: 0x04, RW]

PWM Compare Register [offset: 0x08, RW]

Counter Match Register [offset: 0x0C, RW]

Control Register [offset: 0x100, RW]

Raw Interrupts Status Register [offset: 0xF00, RO]

Reflects the status of interrupts trigger conditions detected (raw, prior to masking).

• to: Time-out Flag
• cp: Capture Flag
• match: Match Flag

Masked Interrupts Status Register [offset: 0xF04, RO]

Similar to RIS but shows the state of the interrupt after masking. MIS register is always RIS & IM.

Interrupts Mask Register [offset: 0xF08, RW]

Disabling/ENabling an interrupt source.

Interrupt Clear Register [offset: 0xF0C, RW]

Writing a 1 to a bit in this register clears the corresponding interrupt state in the RIS Register.

ef_tcc32's Issues

read wrong register instead of counter

There is a typo that causes reading the period address (0x00) value instead of counter address (0x10) value.
https://github.com/shalan/ms_tmr32/blob/main/src/rtl/ms_tmr32_wb.v#LL175C1-L176C1

EF_TCC32 missing/wrong views for IP packaging

1. There are fw and bus_wrapper files, although the json file has a generic bus, which means IPM will overwrite these files
2. There's no hdl/rtl/design hierarchy, should be hdl/rtl

Modes of Operation documentation error

The modes of operation table states that in the Event Capture mode only cp_en need to be enabled but tmr_en should also be enabled for the capture mode to work.

typo in rtl documentation

The capture event type is reversed

EF_TCC32/hdl/rtl/design/EF_TCC32.v

Line 51 in c8c1160

+ cp_event : 1: negedge, 2: posedge, 3: both

it should be

+ cp_event : 1: posedge, 2: negedge, 3: both