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View Code? Open in Web Editor NEWA 32-bit Timer/Counter/Capture Soft IP (Verilog)
License: MIT License
A 32-bit Timer/Counter/Capture Soft IP (Verilog)
License: MIT License
There is a typo that causes reading the period address (0x00) value instead of counter address (0x10) value.
https://github.com/shalan/ms_tmr32/blob/main/src/rtl/ms_tmr32_wb.v#LL175C1-L176C1
The modes of operation table states that in the Event Capture mode only cp_en
need to be enabled but tmr_en
should also be enabled for the capture mode to work.
fw
and bus_wrapper
files, although the json file has a generic bus, which means IPM will overwrite these fileshdl/rtl/design
hierarchy, should be hdl/rtl
The capture event type is reversed
EF_TCC32/hdl/rtl/design/EF_TCC32.v
Line 51 in c8c1160
it should be
+ cp_event : 1: posedge, 2: negedge, 3: both
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