fpgadeveloper / microzed-custom-ip

Custom IP project for the MicroZed

microzed-custom-ip

Custom IP project for the MicroZed

Requirements

This project is designed for Vivado 2020.2. If you are using an older version of Vivado, then you MUST use an older version of this repository. Refer to the list of commits to find links to the older versions of this repository.

• Vivado 2020.2
• MicroZed 7Z010

Description

This project instantiates a custom IP peripheral that interfaces to the Zynq PS as an AXI-lite slave. The custom IP contains a multiplier module that connects to read/write registers which can be accessed by the PS. The project is designed for and tested on the MicroZed board.

Installation of MicroZed board definition files

To use this project, you must first install the board definition files for the MicroZed into your Vivado installation.

The following folders contain the board definition files and can be found in this project repository at this location:

https://github.com/fpgadeveloper/microzed-custom-ip/tree/master/Vivado/boards/board_files

• microzed_7010
• microzed_7020

Copy those folders and their contents into the C:\Xilinx\Vivado\2020.2\data\boards\board_files folder (this may be different on your machine, depending on your Vivado installation directory).

Troubleshooting

Check the following if the project fails to build or generate a bitstream:

1. Are you using the correct version of Vivado for this version of the repository?

Check the version specified in the Requirements section of this readme file. Note that this project is regularly maintained to the latest version of Vivado and you may have to refer to an earlier commit of this repo if you are using an older version of Vivado.

2. Did you follow the Build instructions in this readme file?

All the projects in the repo are built, synthesised and implemented to a bitstream before being committed, so if you follow the instructions, there should not be any build issues.

3. Did you copy/clone the repo into a short directory structure?

Vivado doesn't cope well with long directory structures, so copy/clone the repo into a short directory structure such as C:\projects\. When working in long directory structures, you can get errors relating to missing files, particularly files that are normally generated by Vivado (FIFOs, etc).

License

Feel free to modify the code for your specific application.

Fork and share

If you port this project to another hardware platform, please send me the code or push it onto GitHub and send me the link so I can post it on my website. The more people that benefit, the better.

About us

This project was developed by Opsero Inc., a tight-knit team of FPGA experts delivering FPGA products and design services to start-ups and tech companies. Follow our blog, FPGA Developer, for news, tutorials and updates on the awesome projects we work on.

microzed-custom-ip's Issues

trouble instantiating vhd files into peripheral.

I am trying to follow the tutorial: http://www.fpgadeveloper.com/2014/08/creating-a-custom-ip-block-in-vivado.html#comment-61211. I do steps 2-5. The line where I found reg_data_out <= slv_reg1; is within this block of code in my_multiplier_v1_0_S00_AXI.v:
always @(*)
begin
if ( S_AXI_ARESETN == 1'b0 )
reg_data_out <= 0;
end
else
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0 : reg_data_out <= slv_reg0;
2'h1 : reg_data_out <= multiplier_out; // changed from reg_data_out <= slv_reg1, N Harrison 6/24.
2'h2 : reg_data_out <= slv_reg2;
2'h3 : reg_data_out <= slv_reg3;
default : reg_data_out <= 0;
endcase
end
end

I change it in step 5. However, I cannot follow step 6. I do not see where “slv_reg1” needs to be replaced with with “multiplier_out” and when I save, I do not notice that the “multiplier.vhd” file has been integrated into the hierarchy (step 8).

Can you please post a copy of your my_multiplier_v1_0_S00_AXI.v file so i can compare to my own?