hamsternz / fpga_displayport Goto Github PK

Elephel have created an open source simulation of the GTX / GTP primitives inside the Xilinx parts. You can find more information here -> https://blog.elphel.com/2015/07/gtx_gpl-free-software-verilog-module-to-simulate-a-proprietary-fpga-primitive/

They used it for testing / developing their open source SATA core.

It would be good to see if we could get the DisplayPort core running in simulation on this.

VHDL is poorly supported by the open source toolchains. Verilog is much better supported.

It would be really awesome if this core was in Verilog instead of VHDL :-P

Then lots of the DisplayPort core could be simulated in Icarus or Verilator to formally proven with something like Yosys.

This is probably a prerequisite for #2.