isotel / mixedsim

Hardware Design Tool - Mixed Signal Simulation with Verilog

Hardware Design Tool - Mixed Signal & Domain Simulation

Designing embedded applications typically involves analog, digital worlds, and embedded code. To be able to verify the concepts we strive for simulation tools that could verify all the worlds together, not only as a mixed-signal simulation but also to be able to include Verilog VHDL, as well as Embedded C code.

More info about the project: http://www.isotel.eu/mixedsim

Content

• Eagle to Spice: Simulate existing (real) schematics instead of redrawing parts of it

• Yosys Verilog synthesis library for ngspice, and ltspice

• Mechatronis Example and visualization using Blender

• NgSpice Simulator as a Development Framework for Algorithm & Embedded Firmware Developers

Motivation: Standard ngSpice Model Library

Motivation has started to collect, modify, repair and verify freely available spice models into a common library.

Got interested to join, just open a case on github or contact me directly

mixedsim's Issues

LTspice convergence issues

Weird issues with LTspice and counter example, it doesn't converge neither for yosys cmos primitives, nor ltspice digital primitives.