Store instructions do not have targets, so they aren't freed from the reservation station. Need to think about logic to free store instructions from reservation station
tentatively keep the interface of stage_id the same as project 3 and use the approach in project 3 to connect ROB (previously it was stage_wb) to stage_id which contains regfile
pipeline the memory accesses to be back-to-back to take advanage of pipelining
the current Tomasulo should just handle
RS doesn't remove t1 and t2 on allocate if there is a CDB/ROB match (aestheic, doesn't affect correctness)
Block 1 on RS can be removed
Increase the number of ALUs, Multipliers, possibly loads and stores?
Don't have a branch predictor
first cycle pass through for instruction buffer
The RS and FU waits for CDB broadcast/acknowledge to turn the step function low, instead of having a pulse that immediately goes low. For future optimization, implement additional logic to enable pulses.
It should be put in the pipeline because both ROB and CDB needs output from the priority selector to decide which completed functional unit output to copy/broadcast