josephhanjl / riscv_ooo Goto Github PK

Store instructions do not have targets, so they aren't freed from the reservation station. Need to think about logic to free store instructions from reservation station

Reserve 0th ROB as the empty ROB

Everything before a load or a store completes until a load or a store is dispatched. This ensures no control hazard

We don't have memory latency

• pipeline the memory accesses to be back-to-back to take advanage of pipelining
• the current Tomasulo should just handle
  RS doesn't remove t1 and t2 on allocate if there is a CDB/ROB match (aestheic, doesn't affect correctness)
  Block 1 on RS can be removed
  Increase the number of ALUs, Multipliers, possibly loads and stores?
  Don't have a branch predictor
  first cycle pass through for instruction buffer

Does map table get updated combinationally or on the next clock cycle

Tentatively 8 (the 0th is reserved so 7 available) according to the lecture slides. Asked prof during OH. Make it parameterized later

The RS and FU waits for CDB broadcast/acknowledge to turn the step function low, instead of having a pulse that immediately goes low. For future optimization, implement additional logic to enable pulses.

STOP EXPANDING INTERFACES AND PUT EVERYTHING IN PACKETS. JUST EXPAND PACKETS IN THE SYS_DEF!

Think of ways to avoid this false positive

Just treat the packed packet as a vector and set it to '0

Make busy and issue bits combinational

It should be put in the pipeline because both ROB and CDB needs output from the priority selector to decide which completed functional unit output to copy/broadcast

incorporate the valid bit from the dispatch packet into map table

Have a halt and a clear signal that gets passed to all modules to retain or clear their content

tentatively keep the interface of stage_id the same as project 3 and use the approach in project 3 to connect ROB (previously it was stage_wb) to stage_id which contains regfile

about dispatch checking for dependencies

For unit testing to make sure only one instruction is in the pipeline at any time

Related to store, jump and maybe some unforeseen instructions

Which functional unit do they go to?