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Dear developer,
I need to convert a VHDL file to verilog. I use ./vhd2vl tb_fracn09.vhd tb_fracn09.v command for conversion. I got this error.
ERROR (line 17): undefined type 'string'.
What should I do now? In advance, that VHDL file is tested and works.

I had what appeared to be a simple assignment of the form:

wire <= '-';

Which appears to be something like:
wire <= 1'bx;

It has been a VERY long time since I've done anything with flex or bison, so I think I might see where the string '-' isn't handled:

on line 167 it appears to only handle 0, 1, x, and z, between single quotes. At any rate, it returns the STRING (which I'd guess is 0, 1, x, or z at this point). Presumably it converts the string later in the Bison code. I think I saw that somewhere. It currently looks like a simple "copy" to translate it to verilog, but maybe there could be a check for the - and convert it to the verilog "don't care"? This seems like it COULD occur pretty often. But maybe it doesn't, so it never got handled? Don't know if this is really a bug (I suppose so if VHDL uses this for the "don't care" syntax and vhd2vl doesn't support it) or a feature request, but it appears to be more of a bug.

when i run make within the src folder, this error appears:

cc  -Wall -W -O2 -g -o vhd2vl lex.yy.c vhd2vl.tab.c -lfl -I .
In file included from vhd2vl.l:29:
./def.h:31:3: error: redefinition of 'signal' as different kind of symbol
} signal;
  ^
/Applications/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX10.14.sdk/usr/include/sys/signal.h:390:8: note: previous definition is
      here
void    (*signal(int, void (*)(int)))(int);

i have gcc version 7.3.1 installed

It seems the definition of the struct signal in the file def.h conflicts with the system library

signal douta_ram0 : std_logic_vector(31 downto 0) := 32D"0";

Lines like this return:

syntax error, unexpected NAME at "D" in line 82.

Is there a way to handle the VHDL-2008 init of signals by adding a rule for it?

While running vhdl2vl on various VHDL projects of mine, I've noticed a few problems parsing code that I think shouldn't be too hard to fix and should improve support for existing code considerably.
One of them is when you instantiate a component using the below syntax

ecc : entity work.csi_rx_hdr_ecc port map(
    data => packet_for_ecc,
    ecc => expected_ecc);

It should be safe to ignore the entity work., a workaround (not robust, an example for a standard coding style), is to use sed:
sed 's/entity work\.//'

When attempting to translate a VHDL entity whose PORT declaration contains a user defined type using the technique described here: https://stackoverflow.com/questions/16872950/can-custom-types-be-used-in-port-declaration, there is no way to inform vhd2vl of the custom types and translation fails.

Perhaps an extension that allows users to define packages and entities in the same file would provide a workaround for this?

Hi, currently the tests are failing due to three minor parenthesize inconsistencies. These are not real failures; the "golden outputs" against which the results are diffed ought to be updated.

diff -u '--exclude=Makefile' '--exclude-from=examples/exclude' translated_examples/fifo.v temp/verilog/fifo.v
--- translated_examples/fifo.v  2022-05-11 03:19:46.169628867 +0000
+++ temp/verilog/fifo.v 2022-05-11 03:19:49.881628808 +0000
@@ -74,7 +74,7 @@
   //--- Write address counter -------------
   //---------------------------------------
   assign add_WR_CE = (ifull == 1'b1) ? 1'b0 : (WR == 1'b0) ? 1'b0 : 1'b1;
-  assign n_add_WR = add_WR + 4'h1;
+  assign n_add_WR = (add_WR) + 4'h1;
   always @(posedge clk_WR, posedge rst) begin
     if((rst == 1'b1)) begin
       add_WR <= {5{1'b0}};
diff -u '--exclude=Makefile' '--exclude-from=examples/exclude' translated_examples/test.v temp/verilog/test.v
--- translated_examples/test.v  2022-05-11 03:19:46.169628867 +0000
+++ temp/verilog/test.v 2022-05-11 03:19:49.905628807 +0000
@@ -121,7 +121,7 @@
       3'b101 : code[9:2] <= 8'b11100010;
       3'b010 : code[9:2] <= {8{1'b1}};
       3'b011 : code[9:2] <= {8{1'b0}};
-      default : code[9:2] <= a + b;
+      default : code[9:2] <= (a) + (b);
     endcase
   end

diff -u '--exclude=Makefile' '--exclude-from=examples/exclude' translated_examples/withselect.v temp/verilog/withselect.v
--- translated_examples/withselect.v    1970-01-01 00:00:01.000000000 +0000
+++ temp/verilog/withselect.v   2022-05-11 03:19:49.913628807 +0000
@@ -33,7 +33,7 @@
     endcase
   end

-  assign code1[1:0] = a[6:5] ^ ({a[4],b[6]});
+  assign code1[1:0] = a[6:5] ^ {a[4],b[6]};
   assign foo = {(((1 + 1))-((0))+1){1'b0}};
   assign egg = {78{1'b0}};
   assign baz = {(((bus_width * 4))-((bus_width * 3 - 1))+1){1'b1}};
make: *** [Makefile:33: diff] Error 1

http://doolittle.icarus.com/~larry/vhd2vl/

I still see 2.4 link of 2.5 release.

Please fix.

There are a number of bugs that you can uncover by compiling with ASan (-fsanitize=address) and MSan (-fsanitize=memory with clang).

One of them, from ASan, has an easy fix here: acairncross@f0e1d1e

The others, from MSan, are a bit more involved, but are generally the result of reading fields that aren't always initialized like the op field of expdata. I couldn't figure out exactly what the op field is supposed to contain so haven't got a patch for it.

I think these are the cause of #17 and #15, i.e. vhd2vl has non-deterministic output, although I've only seen the non-determinism appear if you compile with -D_FORTIFY_SOURCE=1 (or 2)