Comments (4)
With the recent wide shift optimization, this now lowers to the following. The register allocation is funky, but the thrust of this issue is fixed, so calling this one done.
main: ; @main
lda 162
sta __rc2
lsr __rc2
lsr __rc2
lsr __rc2
lsr __rc2
ldx __rc2
pha
lda main.digits,x
tax
pla
stx 1024
and #15
tax
lda main.digits,x
tax
stx 1025
ldx #0
txa
rts
main.digits:
.ascii "0123456789\001\002\003\004\005\006"
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Is this the same (class of, similar) issue as #272 ?
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from llvm-mos.
I see. Sorry, then.
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