m1geo / pi5_pcie

A crude reverse engineering of the Pi5 PCIe connector & potential breakout boards.

Pi5 PCIe & M2 NVMe

A crude reverse engineering of the Raspberry Pi 5's FPC PCIe connector & potential breakout board.

OFFICIAL RASPBERRY PI PCIE DOCOUMENTATION CAN BE FOUND HERE: https://datasheets.raspberrypi.com/pcie/pcie-connector-standard.pdf

In this bare-bones project I document a working PCIe pinout talk through my hardware tinkering to get the Raspberry Pi 5's PCIe connected to something. I had only seen Raspberry Pi's boards with their RP2040 and lots of parts on board. My professional experience with PCIe was that it either just goes or it really doesn't. I decided to try and make it do something for no reason other than the technical challenge.

To see what I did, check out my walkthrough of the process on YouTube: Raspberry Pi 5 - Unofficial PCIe Success - Hacking the Pi5's PCIe into life.

Note: This project is a reverse engineering - Please wait for/use the official Raspberry Pi PCIe documentation when using the PCIe FPC

Pi5 PCIe Breakout Board

The board is a quick test board. It could definitely be improved :)

Pi5 M.2 NVMe Breakout Board

pi5_pcie's Issues

Hat ID EEPROM

Hi,

I notice you connect the i2c pins to SMDAT and SMCLK but i think most likely these must be connected to an i2c eeprom chip.

https://hackaday.io/project/167888-not-quite-useless-raspberry-pi-replacement/log/170018-raspberry-pi-hat-id-eeprom-details

https://github.com/raspberrypi/hats

A board can only be called a HAT if:

It conforms to the basic add-on board requirements
It has a valid ID EEPROM (including vendor info, GPIO map and valid device tree information).

I2C

I suspect P3+P4 are I2C and used to communicate with the RP2040 seen on the prototype M.2 HAT. The BCM2712 has two pins muxed to the I2C peripheral and they're named PCIE_SCL/SDA. It isn't the RP1 either as that has a separate I2C bus.

These two pins are configured with the weak internal pulldown enabled and always read as low. The M.2 HAT presumably has the missing I2C pullup resistors.

114: a1    pd | lo // PCIE_SDA/GPIO14 = SPI_S_MOSI_OR_BSC_S_SDA
115: a1    pd | lo // PCIE_SCL/GPIO15 = SPI_S_SCK_OR_BSC_S_SCL

Should be easy enough to confirm by running pinctrl before & after pulling the pins high.

help wanted: what is the purpose of optional block?

I was wondering what is the purpose of this optional block (oscillator):

I guess it would be possible to get full power via FPC connector and connection to Raspberry Pi header 5v is optional?

Testing with i225

Hi there,

Is there any chance you can try an intel i225 with your extension can see if it works.
I am specifically interested since you are reversing the polarity of the reset signal.

Thank you

PCIe Lane inter-pair reversal

The prototype M.2 HAT doesn't appear to have crossed PCIE_RX0P/N pairs, so I suspect I have them around the wrong way. It works on hardware both ways, so at least one end autodetects. Thus, can't rely on the "working" to be the indicator, and now using the PCB traces to inform.

[AltText: Quick drawing showing the RX pair lanes are swapped on the Pi5 connector, confirming there is no twist on the M.2 hat]