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advanced-computer-architecture

Code for Advanced Computer Architecture

aes

Advanced encryption standard implementation in verilog.

awesome-cryptography

A curated list of cryptography resources and links.

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

basic-simd-processor-verilog-tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

bayesianoptimization

A Python implementation of global optimization with gaussian processes.

biriscv

32-bit Superscalar RISC-V CPU

cecs-561

Hardware/Software Co-Design

cmos_asic_design-lab

Contains the all the assignments of CMOS ASIC Design Lab

co-design

Software/Hardware Co-design for Deep Learning.

combinational-bnn

System Verilog code describing a fully combinational binarized neural network.

command_line_perl

This Repository contains the some basic illustrations of Command Line Perl (CPL) useful in reading the files with respect to Chip Design

convolution_network_on_fpga

CNN acceleration on virtex-7 FPGA with verilog HDL

cornell-moe

A Python library for the state-of-the-art Bayesian optimization algorithms, with the core implemented in C++.

cs231n-project

CNN accelerator

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

digital-system-design-and-generation

Digital System Design and Generation - System Verilog Projects

digital_logic_verification_using-systemverilog

Contains Small projects on Verification Using System Verilog

digital_logic_verification_using-uvm

Contains simple projects on UVM

digital_system_design-lab

Contains all the basic Digital Circuits which are written in Verilog HDL

drivers

ec551

fpga-sparse-matrix-mult

A sparse matrix multiplication FPGA architecture which acts as a 'coprocessor'.

fpga_test_soc

A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)

gnn-hardware-acceleration-paper

This repo is to collect the state-of-the-art GNN hardware acceleration paper

gnn-tutorial

Graph Neural Network Tutorial

hw

RTL, Cmodel, and testbench for NVDLA

hw_sw

Hardware Software Co-Design Course Project

hwasim

HWASim is a simulator for heterogeneous systems with CPUs and Hardware Accelerators (HWAs). It is released with the DASH memory scheduler paper that appeared at ACM TACO 2016: https://users.ece.cmu.edu/~omutlu/pub/dash_deadline-aware-heterogeneous-memory-scheduler_taco16.pdf

int_fp_mac

INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.