Code for advanced computer architecture
The labs use trace driven simulations/committed instructions and thus the labs are meant to count number of cycles taken to show efficiency of different implementations. No data is being passed aroudn in the traces
Lab_1: Introduction, basic counting number of instructions, instructions type etc
Lab_2: Implement an in-order superscalar pipeline with perfect and G-share branch predicition
Lab_3: Out of order superscalar pipeline. Implemented ROB, RAT, Scheduler. Also wrote interface between componenets besides FETCH, DECODE and EXEQ
Lab_4: Evaluating DRAM, L2, L1 cache/memory access time. Also implementing multi-core with seperate L1-caches