Master ACK not detected during adr arbitration about i3c-slave-design

[pkimelman-nxp]

The SDA_r is correctly registering a 0, so that is not a problem. State (or really state_base) only changes on the falling edge, but your state moves to 0 on the rising. This means that state!=state_base at that point, which likely means STOP_r got set. You need to look at your simulation pin equations as the sim likely sees a very short duration change of SDA_in which triggers STOP_r (edge sensitive to SDA rising). This can happen if you are using ?: in your pin_SDA_in equation on the outside as well as due to other factors in how you made that Master ACK work. But, you will see that just after the SCL rising, it detects STOP. So, this is a simulation setup problem (and/or a master model problem).

[sdolezal]

Yes, you're right - I can see the slave detecting "stop" on the rising edge of SCL, which is strange, since I expected it to detect this only on rising edge of SDA. But I've seen glitches on SDA today when using a different simulator, so it's probably my sim model causing this. I will have to tweak the simulator to be sure.

[sdolezal]

Ok, I've seen it clearly in the sim - this problem is definitely on my side, like you described - Many Thanks!