Comments (2)
pkimelman-nxp
commented on July 28, 2024
Is has been tested in the past, but no user is using it without MDB, so it is possible something got broken.
It should release/handoff after the SCL rising edge of the Controller ACK, as you say.
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tsuhuai
commented on July 28, 2024
I have modified 'i3c_sdr_slave_engine.v' , and the simulation result is OK.
from i3c-slave-design.
Related Issues (20)
- Are unhandled CCCs passed through to the mr_* bus? HOT 2
- SDA negated prematurely during ACK HOT 2
- Request to have source uploaded as separate files instead of a zip file HOT 6
- Is support for "read current address" missing? HOT 1
- Unsupported syntax in Verilog 2005 HOT 4
- Latches inferred on dma_r[5:4] HOT 2
- MAP_DA_AUTO[12:8] = 0 causes compile error HOT 7
- Push pull and open drain HOT 3
- i2c_spike_ok error HOT 7
- Wrong parameter default MAP_DA_AUTO HOT 2
- Master ACK not detected during adr arbitration HOT 3
- CCCs are not being executed HOT 5
- The function of HJ? thank you very much HOT 1
- About REG_RULES[1] bit
- "i3c_time_control" module is missing HOT 3
- GETPID CCC not executed HOT 1
- i3c_autonomous_reg.v HOT 2
- ACK behavior of I3C target before they are configured into I3C mode.
- the difference between PIN_MODEL == `PINM_COMBO and PINM_REG HOT 3
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