pablomarx / rodinia

AGM bitstream utilities and decoded files from Supra

Contents

• bitstream Scripts to unpack and explain a SPI bitstream file
• supra Tools to decode files from Supra distribution, and copies of those decoded files
• examples Example projects using yosys and Supra's af tool.
• nextpnr Work in progress driver for nextpnr-generic targetting AG1KLPQ48.

rodinia's Issues

Include PLL example in Blinky

I'm happy I can finally start playing with the AG1KLP chip using your examples as a basis.

But there's one thing that darkens my day. It seems I can't make AF place&route designs with PLL instantiated. Yosys does its job, but AF then either crashes with exception (alternatively sefgaults), or stops, telling that "Slice pll|clkout0~ALTA_GCLK is not yet packed, ignored for placement".

I understand there must be some tech-related strict requirements on global clock nets and pll outputs handling, so the Yosys and AF must include required primitives (alta_gcksel, etc). But when I naively add alta_io_gclk buffer to the PLL output in my sources, I get AF failing to read DB design in place&route, because it did produce intermediate files with syntax errors "unexpected '(', expecting ID at ./output/alta_db/filtered.vx" where it inserted unnamed instance of alta_io_gclk after the alta_gclksel.

I hope you can shed some light on the issue, and include the example of valid PLL instantiation with Yosys, conforming to the chip's requirements. I did try suggested workflow with Quartus, but it seems it's not possible with free Quartus Lite Edition, which doesn't support the design partitions.

About Supra Native mode

Dear pablomarx,

I am a college student and i would like to ask a question is: how can i use Supra "Native" mode to bulid my project but not to use the "compatible" mode to maigrate the project from Quartus. THX!

i have finished my project already in Quartus and i just need to port my code to Supra and use its own compiler(Native Mode). but i dont know how to bulid a project in Supra and add design file to it like what i do in Quartus. I am very appreciated to your help!!!!!

Full replacement for quartus?

How far is this project to be a full replacement for quartus? I am desperately looking for any resources for AG1KLPQ48 - I can see inalta_sim.v that there is declaration of module module alta_spi but when I instantiate it in my design, supra fails during synthesis with Error: Segmentation Fault., it fails both on windows as well on linux. Last messages from supra give a clue:

Error: instance_spi has no corresponding resource in the device, ignored.
Info: instance_spi|Scko is identified as a clock gate signal.

I would like to verify whether this chip has a real SPI IP or if I need to use software/verilog implementation in order to use SPI. In my workflow I am building with portable version of quartus 13.1 & supra 2019.10.b0 on linux cloud with simple HTTP nodejs service running following commands (sed is to suppress randomization):

af -B --setup --mode QUARTUS --design app --device AG1KLPQ48 -X "set DEVICE_FAMILY 1"
for d in *.tcl ; do
  sed -i 's/rand()/0/g' $d
  sed -i 's/set_seed_rand/#set_seed_rand/g' $d
  sed -i 's/\$seed_rand//g' $d
done
quartus_map --read_settings_files=on --write_settings_files=off app -c app
quartus_sh -t af_quartus.tcl
af -B --batch --mode QUARTUS -X "set QUARTUS_SDC true" -X "set FITTING timing_more" -X "set FITTER full" -X "set EFFORT highest" -X "set HOLDX default" -X "set SKEW basic"

What kind of peripherals are included in AG1KLPQ48 (besides of alta_bram, that one is working well for me)?