pothosware / pothoszynq

DMA source and sink blocks for Xilinx Zynq FPGAs

DMA source and sink blocks for Xilinx Zynq FPGAs

The Pothos Zynq support package provides:

• DMA source and sink blocks for zero-copy buffer integration with a Pothos data flow
• a linux kernel module for interfacing with an AXI DMA engine in the programmable logic
• loopback examples in Vivado, Zynq boot files, and documentation to recreate the demo

Layout

• kernel/ - the Pothos AXI DMA support linux kernel module
• driver/ - the Pothos AXI DMA userspace driver with C API
• blocks/ - Pothos framework DMA source and sink blocks
• loopback_microzed/ - example Vivado loopback project and boot files

Dependencies

• Pothos library
• Zynq processor running linux

Building

Configure, build, and install with CMake

Using DMA blocks

insmod pothos_zynq_dma.ko
ls /dev/pothos_zynq_dma*

Licensing information

Use, modification and distribution is subject to the Boost Software License, Version 1.0. (See accompanying file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)

pothoszynq's Issues

FPGA logic to create tuser from stat/ctrl user data

We want to create a AXI DMA channel support "lite" that can deal with tuser without requiring the AXI DMA channel mode which requires additional resources and has S2MM limitations for automatic SG table advancement.

The control bus already forwards arbitrary user data from scatter gather entries and vice-versa for status bus. This can be used with a simple state machine to drive/read-in tuser.

Source/Sink for ADC/DAC interface

Hi,
We have a small data rate ADC and DACs upto 4MSPS which are interfaced with ZYNQ using LVDS channels.
We created the IP which produces ADC Samples over axi-stream interface. Can we use this frame work for data copy from PS to PL and PL to PS? Or its only designed for some computation acceleration blocks to pass data from Pothos framework running in ZYNQ PS.

DMA Performance

Hi, I just found your project and was curious if you've done any performance benchmarking of your driver for data transfer rates between CPU/FPGA? I've been working with the zynq-xdma driver from bmartini and while it works fairly well, it doesn't support scatter/gather so I was curious if that really improves performance or not.
Thanks,
-Austin

user driver needs generic access to SG user fields

pzdud_release/acquire need to deal with start/end flags