Topic: vivado Goto Github
Some thing interesting about vivado
Some thing interesting about vivado
vivado,合肥工业大学2020年《系统硬件综合设计》(《计算机组成原理》课程设计,CPU)的代码与报告;使用Verilog实现全冒险处理机制的MIPS五段流水CPU,支持MIPS-C3的50条指令。
User: 25th-engineer
Home Page: https://blog.csdn.net/u25th_engineer/article/details/108540802
vivado,the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
User: arjun-narula
vivado,FPGA Accelerator for CNN using Vivado HLS
User: changwoolee
vivado, :moneybag: A simplified version of an FPGA bitcoin miner :moneybag:
User: diogofferreira
vivado,Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
User: eugene-tarassov
vivado,Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
Organization: f4pga
Home Page: https://prjuray.rtfd.io
vivado,Machine learning on FPGAs using HLS
Organization: fastmachinelearning
Home Page: https://fastmachinelearning.org/hls4ml
vivado,Introduction to Computer Systems (II), Spring 2021
Organization: fducslg
Home Page: https://fducslg.github.io/ICS-2021Spring-FDU/
vivado,Lenet for MNIST handwritten digit recognition using Vivado hls tool
User: floyedshen
vivado,Image Processing Toolbox in Verilog using Basys3 FPGA
User: gowtham1729
vivado,A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
Organization: hdl-modules
Home Page: https://hdl-modules.com
vivado,Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
Organization: hpcn-uam
vivado,Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
User: hukenovs
vivado,TCL scripts for FPGA (Xilinx)
User: hukenovs
vivado,Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)
User: idoka
Home Page: http://idoka.ru/my-fpga-and-asic-scripts/
vivado,A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
User: ilaydayaman
vivado,A place to keep my synthesizable verilog examples.
User: jeffdecola
vivado,Objective of this project was to emulate a Basketball scoreboard, with timer and two teams scores. See readme for pic and more details. FPGA design with Vivado.
User: jge162
Home Page: https://tinyurl.com/ScoreBoardDemo
vivado,Design and Implementation of a Simple-As-Possible 1 (SAP-1) Computer using an FPGA and VHDL.
User: karenok
Home Page: https://karenok.github.io/SAP-1-Computer/
vivado,Vivado and PetaLinux projects for Zynq EBAZ4205 Board
User: keitetsuworks
vivado,A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA
User: lauchinyuan
vivado,帮助大家进行FPGA的入门,分享FPGA相关的优秀文章,优秀项目
User: leiwang1999
vivado,Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
User: li3tuo4
vivado,HDL support for VS Code
User: mshr-h
vivado,Nvidia/Mellanox Innova-2 Flex Open Programmable SmartNIC Setup and Usage Notes for XCKU15P FPGA Development
User: mwrnd
vivado,Verilog Implementation of an ARM LEGv8 CPU
User: nxbyte
vivado,Notes on the Red Pitaya Open Source Instrument
User: pavel-demin
Home Page: http://pavel-demin.github.io/red-pitaya-notes/
vivado,Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
User: sgherbst
vivado,车牌识别,FPGA,2019全国大学生集成电路创新创业大赛
User: starrynightzyq
vivado,16-bit Adder Multiplier hardware on Digilent Basys 3
User: suoglu
vivado,VHDL course at Brno University of Technology
User: tomas-fryza
vivado,使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例
User: wangxuan95
Home Page: https://gitee.com/wangxuan95/Zynq-Tutorial
vivado,Build Customized FPGA Implementations for Vivado
Organization: xilinx
Home Page: http://www.rapidwright.io
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