Topic: verilator Goto Github
Some thing interesting about verilator
Some thing interesting about verilator
verilator,Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verification of verilog systems.
User: albaeda
verilator,A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
User: ben-marshall
verilator,VeeR EH1 core
Organization: chipsalliance
verilator,VeeR EL2 Core
Organization: chipsalliance
Home Page: https://chipsalliance.github.io/Cores-VeeR-EL2/html/index.html
verilator,A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
User: dpretet
verilator,SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
User: dpretet
verilator,Introduction to Computer Systems (II), Spring 2021
Organization: fducslg
Home Page: https://fducslg.github.io/ICS-2021Spring-FDU/
verilator,Re-coded Xilinx primitives for Verilator use
User: fredrequin
verilator,Bazel build rules for Verilator
User: kkiningh
verilator,Quasar 2.0: Chisel equivalent of SweRV-EL2
Organization: lampro-mellon
verilator,BOOM's Simulation Accelerator.
User: maxxsoft
verilator,:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
Organization: microdynamics-cpu
verilator,HDL support for VS Code
User: mshr-h
verilator,π This linter plugin for SublimeLinter provides an interface to Verilator (Verilog Simulator)
User: poucotm
verilator,a project to check the FOSS synthesizers against vendors EDA tools
User: rodrigomelo9
verilator,SCARV: a side-channel hardened RISC-V platform
Organization: scarv
verilator,Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster
Organization: semify-eda
verilator,Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
User: sgherbst
verilator,32-bit Superscalar RISC-V CPU
User: ultraembedded
verilator,Various HDL (Verilog) IP Cores
User: ultraembedded
verilator,RISC-V CPU Core (RV32IM)
User: ultraembedded
verilator,Verilator open-source SystemVerilog simulator and lint system
Organization: verilator
Home Page: https://verilator.org
verilator,Extended and external tests for Verilator testing
Organization: verilator
verilator,A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, netxpnr-ecp5, nextpnr-gowin, Amaranth HDL, Silice and Verilator.
User: vmunoz82
verilator,δΈηδΈθ― οΌ ysyx οΌ npc . the repo of the YSYX project . a riscv-64 CPU . writing .
User: wataru030-xiaohei
verilator,A utility for Composing FPGA designs from Peripherals
User: zipcpu
verilator,A collection of debugging busses developed and presented at zipcpu.com
User: zipcpu
verilator,A configurable C++ generator of pipelined Verilog FFT cores
User: zipcpu
verilator,Digital Interpolation Techniques Applied to Digital Signal Processing
User: zipcpu
verilator,SD-Card controller, using either SPI, SDIO, or eMMC interfaces
User: zipcpu
verilator,A wishbone controlled scope for FPGA's
User: zipcpu
verilator,A simple, basic, formally verified UART controller
User: zipcpu
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