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Implementation of a Tensor Processing Unit for embedded systems and the IoT.

License: Other

C 10.90% MATLAB 0.09% Python 5.56% VHDL 82.91% Objective-C 0.54%
assembly embedded-systems fpga fpga-accelerator hardware-acceleration hardware-architectures hardware-description-language hardware-designs internet-of-things iot ip-core linux tensor tensorflow tpu verilog vhdl vivado xilinx zynq

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tinytpu's Issues

Use DSP IP for optimal DSP usage

In Control: Some registers and functions can't be inferred by RTL Synthesis (OPMODE register, PATTERN DETECT), which can be useful.
Direct instantiation is also possible.

Trying to synthesize

Hello,
I'm trying to use this very helpful TPU architecture you provided but i'm kinda confused on several points in the hdl.
i got an error in Quartus, because it doesn't understand std_logic_vector(unsigned(COUNTER_cs) + '1') (Vector added to a single bit)
Thank you for your help, i appreciate
John

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