pulp-platform / carfield Goto Github PK

Add a make debug or similar target to simulate the design with full visibility (+acc and logging all the waves). To be tirggered when only full debug is required

@bluewww

To fix:

• hw/ip/debug_mode/rtl/debug_mode_preload.sv:60: Netlist for always_comb block contains a latch. @maicolciani
• src/per2axi_res_channel.sv:89: Netlist for always_ff block contains a latch. @yvantor
• src/hyperbus_axi.sv:257: Netlist for always_comb block contains a latch. @luca-valente
• core/cva6_clic_controller.sv:43: Netlist for always_comb block contains a latch. @bluewww @alex96295 @niwis

I don't know the cause yet but the reset sequence fails somewhere during isolation

• Fix PULP warm reset
  * [ ] Fix Periph warm reset -> can be done, but no use case for peripheral domain reset
• Fix Security island warm reset
• Fix L2 warm reset

There is an issue with this piece of logic. Since the PULP cluster has a separate CDC destination FIFO due to its different AXI ID widths respect to the rest of the SoC, if one wants to use a very basic Carfield configuration where Cfg.AxiExtNumMst becomes 0, that for has an iterative spanning from 0 to 0-1, and the code does not compile. To mitigate this, as a temporary solution we prevent Cfg.AxiExtNumMst from being zero with this workaround. The "final solution" would be to unify all the AXI IDs so that the PULP cluster does not need a dedicated port and the iterative of that for can freely span from 0 to Cfg.AxiExtNumMst, with a consequent increase in the area of the AXI crossbar that should be investigated.

Line 294 and 295 of carfield_pkg generate synthesis errors:

Error: /home/agarofalo/2023_prj/CARFIELD/CarfieldPD_Intel16/.bender/git/checkouts/carfield-98c7188642667437/hw/carfield_pkg.sv:294: The construct 'string' is not supported in synthesis.
Error: /home/agarofalo/2023_prj/CARFIELD/CarfieldPD_Intel16/.bender/git/checkouts/carfield-98c7188642667437/hw/carfield_pkg.sv:295: The construct 'string' is not supported in synthesis.

Simulation leaves you with these errors

# ** Error: (vsim-7) Failed to open SDF file "./tb/hyp_vip/s27ks0641_verilog.sdf" in read mode.
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-SDF-3445) Failed to parse SDF file "./tb/hyp_vip/s27ks0641_verilog.sdf".
#    Time: 0 ps  Iteration: 0  Region: /tb_carfield_soc/fix/car_vip/sdf_annotation[0]/sdf_annotation[0]
# Mem (          0,          0)
# ** Error: (vsim-7) Failed to open SDF file "./tb/hyp_vip/s27ks0641_verilog.sdf" in read mode.
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-SDF-3445) Failed to parse SDF file "./tb/hyp_vip/s27ks0641_verilog.sdf".
#    Time: 0 ps  Iteration: 0  Region: /tb_carfield_soc/fix/car_vip/sdf_annotation[0]/sdf_annotation[0]
# Mem (          0,          1)
# ** Error: (vsim-7) Failed to open SDF file "./tb/hyp_vip/s27ks0641_verilog.sdf" in read mode.
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-SDF-3445) Failed to parse SDF file "./tb/hyp_vip/s27ks0641_verilog.sdf".
#    Time: 0 ps  Iteration: 0  Region: /tb_carfield_soc/fix/car_vip/sdf_annotation[0]/sdf_annotation[0]
# Mem (          1,          0)
# ** Error: (vsim-7) Failed to open SDF file "./tb/hyp_vip/s27ks0641_verilog.sdf" in read mode.
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-SDF-3445) Failed to parse SDF file "./tb/hyp_vip/s27ks0641_verilog.sdf".
#    Time: 0 ps  Iteration: 0  Region: /tb_carfield_soc/fix/car_vip/sdf_annotation[0]/sdf_annotation[0]

@yvantor

After #245 , the documentaiton will be missing some information.

@yvantor I will do it ASAP, maybe next week. Opening this issue to make the misalignment evident to everybody

• Use https://github.com/pulp-platform/axi/tree/axi_lite_dw_converter/src, wait until it is merged into main in axi

Carfield includes several cores, we should align hartids at system level. Current proposal:

cva6 -> 0,1
Safey -> 8-10
HMR cluster -> 32-43
Spatz cluster -> 64-...

@micprog @yvantor we shall discuss about this

• SPI, I2C, UART are in the same clock domain of the cva6 host in default cheshire
• An alternative is to disable them and route them in the peripheral domain

[EDIT] @alex96295

Test is added in #137 and the secure boot pin becomes meaningful after #108 is merged

@CyrilKoe you can refer to this issue when opening the PR addressing this part of the documentation

Hi，
When I tried to geretate bitstream for vcu128, I ran comman as :

make car-xil-all XILINX_FLAVOR=vanilla VIVADO=vivado VIVADO_MODE=batch

Vivado report:
module 'xilinx_rom_bank_1024x22' not found in
carfield/.bender/git/checkouts/opentitan-818279ef745672fc/hw/ip/prim/rtl/prim_otp_wrap_adv.sv:90

And I find : opentitan/hw/ip/prim_generic/rtl/prim_generic_rom.sv: xilinx_rom_bank_8192x40 is also missing.

Any help?
Thanks.

From the README.md:
"make car-init" should download carfield.
I get this:
bender -d Carfield/test01 checkout
Checkout safety_island ([email protected]:carfield/safety-island.git)
warning: Please ensure the commits are available on the remote or run bender update
error: Failed to checkout given commit in Bender.lock.
Git command (Command { std: cd "Carfield/test01/.bender/git/db/safety_island-faba656b56b385a7" && "git" "tag" "bender-tmp-d0771928a2b850272c7a3d1b2a4a767bfb7c30a9" "d0771928a2b850272c7a3d1b2a4a767bfb7c30a9" "--force", kill_on_drop: false }) in directory "Carfield/test01/.bender/git/db/safety_island-faba656b56b385a7" failed with exit code 128:

fatal: cannot update ref 'refs/tags/bender-tmp-d0771928a2b850272c7a3d1b2a4a767bfb7c30a9': trying to write ref 'refs/tags/bender-tmp-d0771928a2b850272c7a3d1b2a4a767bfb7c30a9' with nonexistent object d0771928a2b850272c7a3d1b2a4a767bfb7c30a9

Right now they are run in the root of the repo. Fix this.

-> Interrupts
-> AXI isolate
-> (If any) fetch_enable etc

Status

• Safety island -> PR#23
• Security island
• Integer cluster
• Floating point cluster
• Cheshire (if any)

Align Bender IPs and point to stable versions. Some IPs that need attention for alignment:

• FPU (cva6, safety_island, spatz)
• iDMA (Cheshire, spatz) -> @yvantor
• CLIC (Cheshire, safety_island) -> @alex96295

@micprog are you on board to keep track of this with me?

IPs under AlSaqr-platform are not readily available. It also makes sense to have all IPs which are used in Carfield to be hosted on pulp-platform (you don't have want random remote locations to suddenly disappear)

Currently the following IPs are affected

• [email protected]:AlSaqr-platform/can_bus.git -> the IP has been made publicly accessible, but still in the AlSaqr platform
• https://github.com/alsaqr-platform/opentitan.git

This issue is a drawback of our systems developed to exist standalone.

The tracer of each of carfield's cores should follow the hart id of the core.

Not on the critical path, but eases debugging

⚠️ Keep track of AXI crossbar scaling when using only one xbar in Cheshire

@anga93 this is important to keep on top of our heads

5488280#diff-f35fdc4f85c5da80dc8c037b48fb5c825ebae91b44bdb39320222c2ed658f8feL193

To be checked

Probably PULP does not print due to wrong driver usage. Need to adapt the UART driver in pulp-runtime (uDMA UART) to use the APB UART currently used in Cheshire.

We integrated an ECC manager in L2, we need a basic test to test functionality (register access, operation)

A unaligned read from CVA6 to any address should result in an load exception.

Currently, a double word load to CAR_SAFETY_ISLAND_SPM_BASE_ADDR + 1 causes the core to lock up.

Propagate this to the top:

https://github.com/pulp-platform/carfield/blob/main/hw/carfield.sv#L1073

• Currently, a (largely) unoptimized flow involves the host to load a binary for a domain into shared SPM or the domain private SPM
• Accelerate this flow with the DMA

• Careful when routing the watchdog timer reset as it is a vital signal
• Better to keep the watchdog disabled by default and then enable it

Currently introduced in the main carfield tb, it will be moved to where it belongs

@yvantor

Atomics support is needed towards every memory inside carfield. Cheshire already instantiates axi_riscv_atomics_structs before the main memory, the debug module and the idma slave port. We need it before the L2SPM.