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bus_pirate's Introduction

Bus Pirate

Bus Pirate

Bus Pirate (TOL-12942)

This is a troubleshooting tool that communicates between a PC and any embedded device over most standard serial protocols, which include I2C, SPI, and asynchronous serial.

Repository Contents

  • /Hardware — All Eagle design files (.brd, .sch)
  • /Production — Production panel file (.brd)
  • /Software — Minimal Python example demonstrating binary mode

Documentation

Product Versions

  • TOL-12942 — Serial protocol troubleshooting tool

Version History

  • v3.6a — Updated main connector wire colors/locations and improved power regulation
  • v36 — Original version produced by SparkFun

License Information

This product is open source!

Please review the LICENSE.md file for license information.

If you have any questions or concerns on licensing, please contact [email protected].

Distributed as-is; no warranty is given.

  • Your friends at SparkFun.

This is a collaboration with Ian Lesnet.

bus_pirate's People

Contributors

brentwilkins avatar robert-hunke avatar

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bus_pirate's Issues

v3.6 Proto Checklist Issues

(1) I think the Standoff drill hits should be part of a device and have a symbol in the SCH. We should use a standoff device with a symbol and a package from the eagle libraries. If we use a standardized device from the eagle library we can insure that the proper keepout and restrict elements are present, tested, and consistent.

(2) In the SCH the symbol for the cable connector uses a GND flag instead of a GND symbol on the GND net.

(3) USB connector currently has the wrong prefix in the Name field

(4) Level shifting IC currently has the wrong prefix in the Name field

(5) USB needs Tnames and Tvalues elements in the SCH

(6) 3.3V and 5V output traces from the vregs both have 20mil vias that are not masked on top or bottom. For testing purposes I only need the bottoms of the vias unmasked. Unless there is reasoning, I think the tops of these vias should be masked.

(7) VCC trace has two 20mil vias that are not masked on top and bottom. I only need one of these vias unmasked on the bottom for testing (either one works for me), and unless there is reasoning, I think the tops of these vias should be masked.

(8) There are two GND vias that are unmasked on the top and the bottom. One is above the 1x5 header and one is to the left of the 2X5 connector. I think that both of these need mask on top and bottom unless there is a reason.

(9) R1, R5, R8 and all of the resistor arrays need some sort of silk in the package.

(10) Logic shifting IC needs a tPlace polarity marker that is outside of the package.

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