Comments (9)
Thanks :)
Would it be possible to add the iCE40 info to the Area usage and maximal frequency section too?
Yes, i have to do that, it would be also usefull.
It also looks like Murax SoC supports the iCE40 FPGA.
Right, tested on the ice40 hx8k-breakout board, also about supporting multiplication on DSP less FPGA, i recently added a iterative multiplication plugin which only use adders (https://github.com/SpinalHDL/VexRiscv#muldiviterativeplugin)
I'm very interested in know how big VexRiscv smallest is on the iCE40. It would also be interested to know the biggest configuration of VexRiscv that will fit on the various iCE40 parts.
I never toke a exact look to the VexRiscv area usage into iCE40, so i don't realy know the usage for this FPGA family, but i will add iCE40 into the synthesis benchmark.
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Updated https://github.com/SpinalHDL/VexRiscv#area-usage-and-maximal-frequency
One thing to know, is that in iCE40, if you want a FF without the LUT, you can't reuse the LUT for something else, and as VexRiscv is doing "much" pipelining, there is some overhead :)
(Most common FPGA allow to reuse the LUT even if the FF isn't using the lut output and most of the time the LUT usage is 2 time higher than the LUT usage)
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@Dolu1990 It would also be really interested to see this on the iCE40 UltraPlus UP5K device. It's a super low power device but has significantly lower performance.
@daveshah1 added support for these parts to icestorm a while black.
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@mithro I will give a try with the up5k ! Do you have some idea about the performance ratio between the ICE40 HX and the UP5K ?
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Murax ->
iCE40 -> 50 Mhz 2313 LC
iCE40Ultra -> 18 Mhz 2313 LC
MuraxFast (more dhrystone/cycle)->
iCE40 -> 49 Mhz 2644 LC
iCE40Ultra -> 21 Mhz 2644 LC
Note that murax is a little bit smaller than before because i had to reduce the GPIO width from 32 to 8 bits to fit the up5k package.
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Is this with the IceCube2 / Radiant or Icestorm?
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All iCE40 numbers on the readme/here are from icestorm. I remember that a 1 years ago when i give some try with icecube2, i got up to 50 % timings improvment on VexRiscv, but maybe that was a special case, i never tried with Murax.
What is the delta between those tools from your experience ?
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I would say Radiant/iCEcube2 is about 30% better than the icestorm flow for a typical application.
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This all looks good! Closing the issue.
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Related Issues (20)
- CPU exception signal HOT 3
- Regarding the result of dhrystone with TCM HOT 6
- debug HOT 1
- Fetch dosen't performed correctly in the simulation of Murax SOC.(+Custom instructions are executed in unexpected time.) HOT 1
- Instructions to save/restore register to stack is taking 2 clock each HOT 12
- DE0-Nano Board with VexRiscV: IO and Fit Design Issues Including Specific Command Used HOT 3
- Adding VexRiscV as a dependency HOT 2
- Data Stream in/out SoC <-> FPGA HOT 6
- FPU plugin to GenFull.scala HOT 3
- EU Funding HOT 3
- Compile C code and run bare metal cycle accurate simulation HOT 3
- Debug instructions executed twice HOT 5
- Exit cycle accurate simulation HOT 1
- Problems with adding FPU in Briey HOT 5
- Problem about how to compile the software that can be used in Vexriscv with FPU HOT 10
- How to use printf function? HOT 10
- About the Csr registers in Vexriscv HOT 2
- How to only modify certain one reset kind of specific Reg in vex core. HOT 1
- How to only modify certain one reset kind of specific Reg in vex core.
- AxiCrossBar with Standard Axi4 Interface in Briey HOT 15
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