Comments (6)
This is due to a conflict between sbt
and Ubuntu 18.04. Workaround: sbt/sbt#2295 (comment)
from vexriscv.
Same than for the other issue, i made a new ubuntu 18.04 vm, and everything worked fine. I can't reproduce your issue. (openjdk 8)
Anyway, the current VexRiscv master commit doesn't need to build the SpinalHDL library.
Also, you don't need to install Scala :) SBT will download scala himself.
from vexriscv.
Is it ok to close the issue ?
from vexriscv.
I'm trying it again on a fresh install. The behavior I'm seeing at the moment is that sbt "run-main vexriscv.demo.GenFull"
gives no output but does spawn a java
binary that uses a lot of CPU and doesn't exit when I hit Control-C.
xobs@Cuboid:~$ java -version
openjdk version "1.8.0_171"
OpenJDK Runtime Environment (build 1.8.0_171-8u171-b11-0ubuntu0.18.04.1-b11)
OpenJDK 64-Bit Server VM (build 25.171-b11, mixed mode)
xobs@Cuboid:~$
from vexriscv.
You are doing this command in the root of the VexRiscv repository right ?
Maybe the ubuntu on windows is broken ? I never used it, i don't realy know.
The issue that i have is that i can't reproduce the issue.
Maybe you can give a try on raw windows ?
What happend if you just try the sbt command without arguments ?
from vexriscv.
It does work after a reinstall. Apologies, I must have somehow had a corrupted Ubuntu 18.04 install. Thank you for your support.
from vexriscv.
Related Issues (20)
- CPU exception signal HOT 3
- Regarding the result of dhrystone with TCM HOT 6
- debug HOT 1
- Fetch dosen't performed correctly in the simulation of Murax SOC.(+Custom instructions are executed in unexpected time.) HOT 1
- Instructions to save/restore register to stack is taking 2 clock each HOT 12
- DE0-Nano Board with VexRiscV: IO and Fit Design Issues Including Specific Command Used HOT 3
- Adding VexRiscV as a dependency HOT 2
- Data Stream in/out SoC <-> FPGA HOT 6
- FPU plugin to GenFull.scala HOT 3
- EU Funding HOT 3
- Compile C code and run bare metal cycle accurate simulation HOT 3
- Debug instructions executed twice HOT 5
- Exit cycle accurate simulation HOT 1
- Problems with adding FPU in Briey HOT 5
- Problem about how to compile the software that can be used in Vexriscv with FPU HOT 10
- How to use printf function? HOT 10
- About the Csr registers in Vexriscv HOT 2
- How to only modify certain one reset kind of specific Reg in vex core. HOT 1
- How to only modify certain one reset kind of specific Reg in vex core.
- AxiCrossBar with Standard Axi4 Interface in Briey HOT 15
Recommend Projects
-
React
A declarative, efficient, and flexible JavaScript library for building user interfaces.
-
Vue.js
🖖 Vue.js is a progressive, incrementally-adoptable JavaScript framework for building UI on the web.
-
Typescript
TypeScript is a superset of JavaScript that compiles to clean JavaScript output.
-
TensorFlow
An Open Source Machine Learning Framework for Everyone
-
Django
The Web framework for perfectionists with deadlines.
-
Laravel
A PHP framework for web artisans
-
D3
Bring data to life with SVG, Canvas and HTML. 📊📈🎉
-
Recommend Topics
-
javascript
JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
-
web
Some thing interesting about web. New door for the world.
-
server
A server is a program made to process requests and deliver data to clients.
-
Machine learning
Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
-
Visualization
Some thing interesting about visualization, use data art
-
Game
Some thing interesting about game, make everyone happy.
Recommend Org
-
Facebook
We are working to build community through open source technology. NB: members must have two-factor auth.
-
Microsoft
Open source projects and samples from Microsoft.
-
Google
Google ❤️ Open Source for everyone.
-
Alibaba
Alibaba Open Source for everyone
-
D3
Data-Driven Documents codes.
-
Tencent
China tencent open source team.
from vexriscv.